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Revision History
Date
August 2006
August 2005
May 2005
March 2005
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
36
®
®
Intel
IXP45X and Intel
Revision
Section
2.1.1,
ports from six to three. (CCR 1977120)
Section
3.8.2.1: Updated endian operation information (CCR1973155)
Table 99, "Memory
Section
6.1.3,
information regarding the MDI Interface (CCR1970478)
Section
11.2.1: Updated software read/write information (CCR1977819)
Section
11.2.2.8: Updated initialization information
Section
12.1: Updated overview paragraph (CCR2076121)
004
Section
12.5.11: Clarified software disable feature (CCR1976679)
Section
15.4: Updated GPIO example (CCR2039084)
Section
21.5.1: Added note to clarify SCL operation (CCR2002036)
Removed SS-SMII references since this feature is not supported (CCR1980266)
Updated 'Intel® XScale Core' references to be 'Intel XScale
terminology used in the document has changed.
Incorporated specification changes, specification clarifications and document
changes from the Intel
Update (306428-004 and 306428-005)
Section
2.2.11: Corrected number of PMU 32-bit event counters to 4. [SCR4324]
Figure 33
and
UTOPIA polling illustrations. [SCR4323]
Section
11.2.3.5: Clarified MCU behavior when ECC disabled. [SCR4303]
Section
12.4.1.5: Added new description and figures for using I/O wait.
Table 99
and
Section
0), NPE B (interrupt 1), and NPE C (interrupt 2). [SCR4322]
003
Section
16.3.4.3: Added descriptions for MCU PMU event programming.
Section 16.6.1
ESR1, PSR, PMR, PECx, and PMSR. [SCR4299]
Table
260: Clarified MCU event types (0 = page miss, 1 = page hit)
Section
19.4: Added new section:
Section
25.3.1: Added new section:
Added support for Intel
and
Table 97 on page 222
Reordered chapters 6-28 to align with
IXP4XX Product Line of Network Processors Specification Update for chapter
numbering from/to list.
Chapter 12.0, "Expansion Bus Controller"
IXP425 processor.
002
Chapter 13.0, "HSS Coprocessor"
(change bars in figure title only).
Chapter 18.0, "Operating System Timer"
reload register.
Chapter 20.0, "Synchronous Serial Port"
TFL, and ROR bits.
001
Initial release of document.
IXP46X Product Line of Network Processors—Revision History
Description
Section
2.1.3,
Section
4.0: Updated the number of supported SMII
Map": Updated notes (CCR1975264)
Section
6.2.52,
Table
105, and
®
IXP4XX Product Line of Network Processors Specification
Figure
34: Corrected UTP_OP_ADDR and UTP_IP_ADDR values in
17.4: Corrected multiple text references for NPE A (interrupt
through
Section
16.6.5: Corrected physical address values for ESR0,
"Theory of Operation (Auxiliary
"Operand
®
IXP455 Network Processor, including
.
Chapter 2.0
changed text from IXP4XX processor to
corrected signal names in certain timing diagrams
added note about predictable operation of
enhanced descriptions of EFWR, STRF, RFL,
Table
106: Added clarifying
®
Processor'. Only the
Snapshots)".
Restrictions".
Figure 3 on page 47
topic order. See the Intel
August 2006
Order Number: 306262-004US
®
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