Miscellaneous Instruction Timing; Thumb Instructions; Optimization Guide; Introduction - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
3.9.4.10

Miscellaneous Instruction Timing

Table 94.

Exception-Generating Instruction Timings

Mnemonic
SWI
BKPT
UNDEFINED
Table 95.

Count Leading Zeros Instruction Timings

Mnemonic
CLZ
3.9.4.11

Thumb Instructions

In general, the timing of Thumb instructions are the same as their equivalent Intel
StrongARM
• If the equivalent Intel
page
cycles. This is due to the branch latency penalty. (See
• If the equivalent Intel
page
cycle. This is due to the branch latency penalty. (See
• A Thumb BL instruction when H = 0 will have the same timing as an Intel
StrongARM
The mapping of Thumb instructions to Intel
the ARM* Architecture Reference Manual.
3.10

Optimization Guide

3.10.1

Introduction

This document contains optimization techniques for achieving the highest performance
from the IXP45X/IXP46X network processors' architecture. It is written for developers
who are optimizing compilers or performance analysis tools for the devices based on
these processors. It can also be used by application developers to obtain the best
performance from their assembly language code. The optimizations presented in this
section are based on the IXP45X/IXP46X network processors, and hence can be applied
to all products that are based on it.
The IXP45X/IXP46X network processors' architecture includes a super-pipelined RISC
architecture with an enhanced memory pipeline. The instruction set for the IXP45X/
IXP46X network processors is based on the Intel
however, the IXP45X/IXP46X network processors include new instructions. Code
generated for the SA110, SA1100 and SA1110 will execute on the IXP45X/IXP46X
network processors, however to obtain the maximum performance of your application
code, it should be optimized for the IXP45X/IXP46X network processors using the
techniques presented in this document.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Minimum latency to first instruction of exception handler
Minimum Issue Latency
1
*
instructions, except for the cases listed below.
®
StrongARM
184, the "Minimum Issue Latency with Branch Misprediction" goes from 5 to 6
®
StrongARM
184, the "Minimum Issue Latency when the Branch is Taken" increases by 1
*
data processing instruction.
6
6
6
*
instruction maps to one in
*
instruction maps to one in
®
StrongARM
®
StrongARM
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Minimum Result Latency
1
Table 81 on
Table 79 on page 182.)
Table 82 on
Table 79 on page 182.)
®
*
instructions can be found in
*
V5TE architecture;
Developer's Manual
®
189