Host Controller Queue Head Traversal State Machine - Intel IXP45X Developer's Manual

Intel
Figure 65.

Host Controller Queue Head Traversal State Machine

This traversal state machine applies to all queue heads, regardless of transfer type or
whether split transactions are required. The following sections describe each state.
Each state description describes the entry criteria. The Execute Transaction state
(Section 9.14.10.3, "Execute Transaction" on page
requirements for all endpoints.
Transfers" on page 453
page 455
state for endpoints requiring split transactions.
Note: Prior to software placing a queue head into either the periodic or asynchronous
list, software must ensure the queue head is properly initialized. Minimally, the queue
head should be initialized to the following:
• Valid static endpoint state
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Halted
.or.
!Active .AND. Ibit
Advance
Queue
!Active
Section 9.14.12.1, "Split Transactions for Asynchronous
and Section 9.14.12.2, "Split Transaction Interrupt" on
describe details of the required extensions to the Execute Transaction
S t a r t
Fetch QH
!Active
.AND.
!Halted
Active
Execute
Transaction
!Active
Write Back
QTd
Follow QH
Horizontal Pointer
444) describes the basic
!Active .AND. !Halted
Active
4508-01
August 2006
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