Status Register/Control Register - Intel IXP45X Developer's Manual

®
PCI Controller—Intel IXP45X and Intel
10.5.2.2

Status Register/Control Register

Register Name:
Block
0xC00000
Base Address:
Contains the Command and Status registers as specified in the PCI
Register Description:
2.2 Local Bus Specification
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
Detected Parity Error. Set when this device detects a parity error on the
31 DPE
bus even when parity handling is disabled. Writing a 1 to this bit clears it.
Signaled System Error. Set when this device generates a System Error
30 SSE
PCI_SERR_N. Writing a 1 to this bit clears it.
Received Master Abort. Set by this device as a Master when its transaction
29 RMA terminates due to a master abort (except for special cycles). Writing a 1 to
this bit clears it.
Received Target Abort. Set by this device as a Master when its transaction
28 RTA
is terminated due to a target abort. Writing a 1 to this bit clears it.
Signaled Target Abort. Set by this device as a Target when it terminates a
27 STA
transaction with a target abort. Writing a 1 to this bit clears it.
26:2
DEVSEL Defines the DEVSEL speed for this device. Set to medium.
5
Master Data Parity Error. Set by this device as a Master if PER (bit 6) is set
24 MDPE and this device either asserted the PCI_PERR_N signal or saw
PCI_PERR_N asserted for one of its data phases.
23 FBBC Fast Back-to-Back Capable.
22 UDF User Definable Features supported. 0 = not supported
66MHZ capable. Indicates if this device is capable of 66MHz operation.
21 66MHZ
1 = 66MHz capable.
20 CLI Capabilities List Indicator, Not supported
19:1
- reserved
0
Fast Back-to-Back Enable. When set to a 1 enables the device to generate
9 FBBE
fast back-to-back cycles to different targets as a Master.
System Error Enable. When set to a 1, enables the PCI_SERR_N output
8 SER
driver. 0 disables the driver.
Stepping Control. When set to a 1, enables address stepping on the bus.
7 SC
This feature not supported.
Parity Error Response. When set to a 1, enables reporting of parity errors
6 PER on PCI_PERR_N. When set to 0, parity errors not reported on PCI_PERR_N
but the DPE bit (bit 31) is still set.
Palette Snoop Enable. When set to a 1, enables VGA palette snooping.
5 PSE
This feature not supported.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
Offset Address
(Reserved)
pci_srcr (Sheet 1 of 2)
Description
®
Intel IXP45X and Intel
pci_srcr
0x04
Reset Value
8 7 6
Reset
Value
01
00
®
IXP46X Product Line of Network Processors
0x02a00000
Access: (See below.)
5 4 3 2 1 0
PCI AHB
Access Access
0 RW1C RW1C
0 RW1C RW1C
0 RW1C RW1C
0 RW1C RW1C
0 RW1C RW1C
RO RO
0 RW1C RW1C
1 RO RO
0 RO RO
1 RO RW
0 RO RO
RO RO
0 RW RW
0 RW RW
0 RO RO
0 RW RW
0 RO RO
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