Intel IXP45X Developer's Manual page 34

244 Typical Baud-Rate Settings ...................................................................................... 753
245 UART Transmit Parity Operation ............................................................................... 755
246 UART Receive Parity Operation ................................................................................. 755
247 UART Word-Length Select Configuration .................................................................... 755
248 UART FIFO Trigger Level.......................................................................................... 761
249 Register Legend ..................................................................................................... 761
250 UART Registers Overview ........................................................................................ 762
251 UART IDD Bit Mapping ............................................................................................ 767
252 Register Legend ..................................................................................................... 779
253 Register Summary .................................................................................................. 779
254 Occurrence Events.................................................................................................. 789
255 Duration Events ..................................................................................................... 790
256 Register Legend ..................................................................................................... 793
257 PMU Register Table ................................................................................................. 793
258 AHB North PMU Mapping ......................................................................................... 798
259 AHB South PMU Mapping ......................................................................................... 798
260 Event Mux Programming ......................................................................................... 799
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261 Intel XScale Processor Interrupt Mapping ................................................................ 804
262 Register Legend ..................................................................................................... 811
263 Interrupt Controller Memory Mapped Registers ........................................................... 811
264 Register Legend ..................................................................................................... 821
265 Register Summary .................................................................................................. 821
266 System Time Clock Rates ........................................................................................ 834
267 Register Legend ..................................................................................................... 836
268 Register Summary Table ......................................................................................... 837
269 Register Summary .................................................................................................. 838
270 Texas Instruments* Synchronous Serial Frame Format................................................ 859
271 Motorola* SPI Frame Format.................................................................................... 861
272 National Microwire* Frame Format ............................................................................ 862
273 SSP Serial Port Register Summary ............................................................................ 863
274 Register Legend ..................................................................................................... 864
275 Motorola* SPI Frame Formats for SPO and SPH Programming....................................... 867
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276 I C Bus Definitions ................................................................................................. 876
277 Modes of Operation................................................................................................. 878
278 START and STOP Bit Definitions................................................................................ 879
279 Master Transactions ................................................................................................ 887
280 Slave Transactions.................................................................................................. 890
281 General Call Address Second Byte Definitions ............................................................. 892
282 Register Legend ..................................................................................................... 897
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283 I C Register Addresses............................................................................................ 897
284 PKE Peripheral Memory Map and Access Information ................................................... 908
285 Register Legend ..................................................................................................... 911
286 Register Summary .................................................................................................. 911
287 EAU Operand Size Restrictions and Assumptions ......................................................... 914
288 Register Legend ..................................................................................................... 915
289 Register Summary .................................................................................................. 915
290 EAU RAM Memory Locations ..................................................................................... 919
291 Register Legend ..................................................................................................... 921
292 Hashing Coprocessor: Register Summary................................................................... 921
293 AHB Queue Manager Memory Map ............................................................................ 928
294 Queue Status Flags................................................................................................. 934
295 Data Validity Cases and Their Handling...................................................................... 936
296 Register Legend ..................................................................................................... 937
297 Register Summary .................................................................................................. 937
298 NPE Coprocessor Error ............................................................................................ 953
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
34
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Intel IXP45X and Intel IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US