Intel IXP45X Developer's Manual page 145

Network processors
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Intel XScale
Processor—Intel
An additional issue for debug is setting up the reset vector trap. This must be done
before the internal reset signal is de-asserted. As described in
(TF,TI,TD,TA,TS,TU,TR)" on page
DCSR must be set prior to de-asserting reset in order to trap the reset vector. There are
two possibilities for setting up the reset vector trap:
• The reset vector trap can be set up before the instruction cache is loaded by
scanning in a DCSR value that sets the Trap Reset bit in addition to the Halt Mode
bit and the hold_rst signal; OR
• The reset vector trap can be set up after the instruction cache is loaded. In this
case, the DCSR should be set up to do a reset vector trap, with the Halt Mode bit
and the hold_rst signal remaining set.
In either case, when the debugger clears the hold_rst bit to de-assert internal reset,
the debugger must set the Halt Mode and Trap Reset bits in the DCSR.
3.6.14.4.2
Loading IC During a Warm Reset for Debug
Loading the instruction cache during a warm reset may be a slightly different situation
than during a cold reset. For a warm reset, the main issue is whether the instruction
cache gets invalidated by the processor reset or not. There are several possible
scenarios:
• While reset is asserted, TRST is also asserted.
In this case the instruction cache is invalidated, so the actions taken to download
code are identical to those described in
on page 143
• When reset is asserted, TRST is not asserted, but the processor is not in Halt Mode.
In this case, the instruction cache is also invalidated, so the actions are the same
as described in
LDIC instruction is loaded into the JTAG IR.
• When reset is asserted, TRST is not asserted, and the processor is in Halt Mode.
In this last scenario, the mini instruction cache does not get invalidated by reset,
since the processor is in Halt Mode. This scenario is described in more detail in this
section.
In the last scenario described above is shown in
August 2006
Order Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
114, the Halt Mode and the Trap Reset bits in the
"Loading IC During Cold Reset for Debug" on page
Intel
"Loading IC During Cold Reset for Debug"
Figure
26.
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
"Vector Trap Bits
143, after the
Developer's Manual
145

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