Cache Considerations - Intel IXP45X Developer's Manual

Intel
struct {
long ia;
long ib;
long ic;
long id;
long ie;
} tdata[IMAX];
ADDRESS preadd = tdata
for (i=0, i<IMAX; i++)
{
PREFETCH(predata+=16);
tdata[I].ia = tdata[I].ib + tdata[I].ic _tdata[I].id] +
tdata[I].ie;
....
tdata[I].ie = 0;
}
In this case, the prefetch address was advanced by size of half a cache line and every
other prefetch instruction is ignored. Further, an additional register is required to track
the next prefetch address.
Generally, not aligning and sizing data will add extra computational overhead.
Additional prefetch considerations are discussed in greater detail in following sections.
3.10.4.2.7 Literal Pools
The IXP45X/IXP46X network processors do not have a single instruction that can move
all literals (a constant or address) to a register. One technique to load registers with
literals in the IXP45X/IXP46X network processors is by loading the literal from a
memory location that has been initialized with the constant or address. These blocks of
constants are referred to as literal pools. See
more information on how to do this. It is advantageous to place all the literals together
in a pool of memory known a literal pool. These data blocks are located in the text or
code address space so that they can be loaded using PC relative addressing. However,
references to the literal pool area load the data into the data cache instead of the
instruction cache. Therefore it is possible that the literal may be present in both the
data and instruction caches, resulting in waste of space.
For maximum efficiency, the compiler should align all literal pools on cache boundaries
and size each pool to a multiple of 32 bytes (the size of a cache line). One additional
optimization would be group highly used literal pool references into the same cache
line. The advantage is that once one of the literals has been loaded, the other seven
will be available immediately from the data cache.
3.10.4.3

Cache Considerations

3.10.4.3.1 Cache Conflicts, Pollution, and Pressure
Cache pollution occurs when unused data is loaded in the cache and cache pressure
occurs when data that is not temporal to the current process is loaded into the cache.
3.10.4.3.2 Memory Page Thrashing
Memory page thrashing occurs because of the nature of DDRI SDRAM. DDRI SDRAMs
are typically divided into four banks. Each bank can have one selected page where a
page address size for current memory components is often defined as 4 k. Memory
lookup time or latency time for a selected page address is currently two to three bus
clocks. Thrashing occurs when subsequent memory accesses within the same memory
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
206
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
"Basic Optimizations" on page 195
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August 2006