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USB 1.1 Device Controller—Intel
Processors
8.5.3.5
Sent STALL (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user
induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation
from the host PC when a STALL handshake is returned automatically. In either event,
the Intel XScale processor does not intervene and the UDC clears the STALL status
when the host sends a CLEAR_FEATURE command. The endpoint operation continues
normally and does not send another STALL condition, even if the UDCCS1[SST] bit is
set.
To allow the software to continue to send the STALL condition on the USB bus, the
UDCCS1[FST] bit must be set again. The Intel XScale processor writes a 1 to the sent
stall bit to clear it.
8.5.3.6
Force STALL (FST)
The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL
handshake to all IN tokens. STALL handshakes continue to be sent until the Intel
XScale processor clears this bit by sending a Clear Feature command.
The UDCCS1[SST] bit is set when the STALL state is actually entered, but this may be
delayed if the UDC is active when the UDCCS1[FST] bit is set. The UDCCS1[FST] bit is
automatically cleared when the UDCCS1[SST] bit is set.
To ensure that no data is transmitted after the Clear Feature command is sent and the
host resumes IN requests, software must clear the transmit FIFO by setting the
UDCCS1[FTF] bit.
8.5.3.7
Bit 6 Reserved
Bit 6 is reserved for future use.
8.5.3.8
Transmit Short Packet (TSP)
The software uses the transmit short packet bit to indicate that the last byte of a data
transfer to the FIFO has occurred. This indicates to the UDC that a short packet or zero-
sized packet is ready to transmit. Software should always check TSP after loading a
packet to determine if more data can be loaded.
Software must not set this bit if a 64-byte packet is to be transmitted. When the data
packet is successful transmitted, the UDC clears this bit.
Register Name:
0 x C800B014
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 1 Control and Status Register
Description:
Access: Read/Write
31
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Intel
UDCCS1
0 x 00000001
Reset Hex Value:
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Developer's Manual
0
1
297
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