Register Legend; Legacy Expansion Bus Register Summary; Non-Legacy Expansion Bus Register Summary - Intel IXP45X Developer's Manual

Table 225.

Register Legend

Attribute
RS
RW
RW1C
Table 226.

Legacy Expansion Bus Register Summary

Address Access
0xC4000000
0xC4000004
0xC4000008
0xC400000C
0xC4000010
0xC4000014
0xC4000018
0xC400001C
0xC4000020
0xC4000024
Table 227.

Non-Legacy Expansion Bus Register Summary

Address Register Name
0xC4000028 EXP_UNIT_FUSE_RESET
0xC400002C EXP_SMIIDLL
0xC4000100 EXP_MST_CONTROL
0xC4000104
and from
External EXP_INBOUND_ADDR
Master (See
note below)
0xC4000108
and from
External EXP_LOCK0
Master (See
note below)
0xC400010C
and from
External EXP_LOCK1
Master (See
note below)
0xC4000120 EXP_PARITY_STATUS
0xC4000124 EXP_SYNCINTEL_COUNT
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
702
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Intel IXP45X and Intel
Legend
Read/Set
Read/Write
Normal Read
Write '1' to clear
Name
RW EXP_TIMING_CS0
RW EXP_TIMING_CS1
RW EXP_TIMING_CS2
RW EXP_TIMING_CS3
RW EXP_TIMING_CS4
RW EXP_TIMING_CS5
RW EXP_TIMING_CS6
RW EXP_TIMING_CS7
RW EXP_CNFG0
RW EXP_CNFG1
Specifies the value of the fuse register.
DLL bits for SMII used by the SMII DLL.
Specifies values for bus arbitration priority, bus
master locking, and external master parity support
Specifies the upper AHB address for inbound
transfers.
This register is intended to facilitate resource
locking for multiple masters
This register is intended to facilitate resource
locking for multiple masters
Specifies the parity error status.
This register is used to set the read latency count
when a Synchronous Intel Device is accessed.
®
IXP46X Product Line of Network Processors—Expansion Bus
Attribute Legend
WO Write Only
NA Not Accessible
Normal Read
RW1S
Write '1' to set
Timing and Control Register for Chip Select 0
Timing and Control Register for Chip Select 1
Timing and Control Register for Chip Select 2
Timing and Control Register for Chip Select 3
Timing and Control Register for Chip Select 4
Timing and Control Register for Chip Select 5
Timing and Control Register for Chip Select 6
Timing and Control Register for Chip Select 7
General-Purpose Configuration Register 0
General-Purpose Configuration Register 1
Description
Controller
Description
Reset Value Attribute
See Register
0xXXXXXXXX
Table
See Register
0x00000000
Table
See Register
0x00000000
Table
See Register
0x00000008
Table
See Register
0x00000000
Table
See Register
0x00000000
Table
See Register
0x00000000
Table
See Register
0x00000000
Table
August 2006
Order Number: 306262-004US