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Register Name:
0 x C800 B018
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 2 Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.5
UDC Endpoint 3 Control/Status Register
The UDC Endpoint 3control status register contains four bits that are used to operate
Endpoint 3, an Isochronous IN endpoint.
8.5.5.1
Transmit FIFO Service (TFS)
The transmit FIFO service bit is be set if one or fewer data packets remain in the
transmit FIFO. UDCCS3[TFS] is cleared when two complete data packets are in the
FIFO.
A complete packet of data is signified by loading 256 bytes or by setting UDCCS3[TSP].
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
300
®
®
Intel
IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Receive short packet (read only).
RSP
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
RNE
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
Force stall (read/write).
FST
1 = Issue STALL handshakes to OUT tokens.
Sent stall (read/write 1 to clear).
SST
1 = STALL handshake was sent.
(Reserved)
(Reserved). Always reads zero.
Receive packet complete (read/write 1 to clear).
RPC
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS
0 = Receive FIFO has less than one data packet.
1 = Receive FIFO has 1 or more data packets.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS2
0 x 00000000
Reset Hex Value:
Bits
UDCCS2
Description
Controller
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
(UDCCS3)
August 2006
Order Number: 306262-004US
0
0
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