Intel IXP45X Developer's Manual page 312

8.5.10.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit's read value is 0.
8.5.10.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, UDCCS8[TUR] generates an interrupt.
UDCCS8[TUR] is cleared by writing a 1 to it.
8.5.10.5 Bit 4 Reserved
Bit 4 is reserved for future use.
8.5.10.6 Bit 5 Reserved
Bit 5 is reserved for future use.
8.5.10.7 Bit 6 Reserved
Bit 6 is reserved for future use.
8.5.10.8 Transmit Short Packet (TSP)
Software uses the transmit short packet to indicate that the last byte of a data transfer
has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized
packet is ready to transmit. Software should always check TSP after loading a packet to
determine if more data can be loaded.
Software must not set this bit if a packet of 256 bytes is to be transmitted. When the
data packet is successfully transmitted, this bit is cleared by the UDC.
Register Name:
0 x C800 B030
Hex Offset Address:
Register Description: Universal Serial Bus Device Controller Endpoint 8Control and Status
Register
Register
Description:
Access: Read/Write
31
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
312
® ®
Intel IXP45X and Intel
(Reserved)
Resets (Above)
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS8
0 x 00000001
Reset Hex Value:
Bits
Controller
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0
August 2006
Order Number: 306262-004US
0
1