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USB 2.0 Host Controller—Intel
• For the very first use of a queue head, software may zero-out the queue head
transfer overlay, then set the Next qTD Pointer field value to reference a valid qTD.
9.14.10.1
Fetch Queue Head
A queue head can be referenced from the physical address stored in the
ASYNCLISTADDR Register
page
380). Additionally, it may be referenced from the Next Link Pointer field of an iTD,
siTD, FSTN or another Queue Head. If the referencing link pointer has the Typ field set
to indicate a queue head, it is assumed to reference a queue head structure as defined
in
Figure 50, "Queue Head Structure Layout" on page
While in this state, the host controller performs operations to implement empty
schedule detection
page
435) and Nak Counter reloads
Counter" on page
conducts the following queries for empty schedule detection:
• If queue head is not an interrupt queue head (i.e. S-mask is a zero), and
• The H-bit is a one, and
• The Reclamation bit in the USBSTS register is a zero.
When these criteria are met, the host controller will stop traversing the asynchronous
list (as described in
page
435). When the criteria are not met, the host controller continues schedule
traversal. If the queue head is not an interrupt and the H-bit is a one and the
Reclamation bit is a one, then the host controller sets the Reclamation bit in the
USBSTS register to a zero before completing this state. The operations for reloading of
the Nak Counter are described in detail in
Counter" on page
This state is complete when the queue head has been read on-chip.
9.14.10.2
Advance Queue
To advance the queue, the host controller must find the next qTD, adjust pointers,
perform the overlay and write back the results to the queue head.
This state is entered from the FetchQHD state if the overlay Active and Halt bits are
set to zero. On entry to this state, the host controller determines which next pointer to
use to fetch a qTD, fetches a qTD and determines whether or not to perform an overlay.
Note that if the I-bit is a one and the Active bit is a zero, the host controller
immediately skips processing of this queue head, exits this state and uses the
horizontal pointer to the next schedule data structure. If the field Bytes to Transfer is
not zero and the T-bit in the Alternate Next qTD Pointer is set to zero, then the host
controller uses the Alternate Next qTD Pointer. Otherwise, the host controller uses the
Next qTD Pointer. If Next qTD Pointer's T-bit is set to a one, then the host controller
exits this state and uses the horizontal pointer to the next schedule data structure.
Using the selected pointer the host controller fetches the referenced qTD. If the fetched
qTD has its Active bit set to a one, the host controller moves the pointer value used to
reach the qTD (Next or Alternate Next) to the Current qTD Pointer field, then performs
the overlay. If the fetched qTD has its Active bit set to a zero, the host controller aborts
the queue advance and follows the queue head's horizontal pointer to the next
schedule data structure. The host controller performs the overlay based on the
following rules:
• The value of the data toggle (dt) field in the overlay area depends on the value of
the data toggle control (dtc) bit (see
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
(Section 9.12.7, "ASYNCLISTADDR; ENDPOINTLISTADDR" on
(Section 9.14.8.3, "Empty Asynchronous Schedule Detection" on
439). After the queue head has been fetched, the host controller
Section 9.14.8.3, "Empty Asynchronous Schedule Detection" on
439.
Intel
404.
(Section 9.14.9, "Operational Model for Nak
Section 9.14.9, "Operational Model for Nak
Table 161 on page
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
405).
Developer's Manual
443
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