Expansion Bus Controller - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
12.0

Expansion Bus Controller

12.1 Overview
The Expansion bus controller provides an interface from the internal AHB in the Intel
IXP45X and Intel
target devices and an interface from external expansion master devices to the internal
AHB. This interface can be used to couple/connect multiple IXP45X/IXP46X network
processors to one another.
The Expansion bus controller includes a 25-bit address bus and a 32-bit wide data path.
The expansion bus controller maps transfers between the internal AHB and external
devices. The expansion bus supports Intel multiplexed, Intel non-multiplexed, Intel
StrataFlash
Motorola* multiplexed, Motorola non-multiplexed, and Texas Instruments* Host Port
Interface (HPI) target devices. The Expansion bus controller also has an arbiter that
supports up to four external devices that can master the Expansion bus. External
masters can also access internal slaves such as the memory controller in the IXP45X/
IXP46X network processors.
Applications having less than 32-bit external target devices may connect to an 8-bit or
16-bit (halfword) interface.
12.2 Feature List
• Outbound transfers (IXP45X/IXP46X network processors are the master to an
external target device)
• Inbound transfers (IXP45X/IXP46X network processors are a target to an external
master)
• Bus tri-state for sideband transfers (External masters accesses to external target
device)
• Arbitration for four external masters with support for an external arbiter
• Eight programmable target chip selects
• Twenty five bits of address; thirty two bits of data
• Supports Intel mode and Motorola mode bus cycles
• Supports Intel StrataFlash
• Supports 66-MHz Synchronous Intel StrataFlash
• Supports 16-bit and 32-bit Micron Flow-Through ZBT (Zero bus turnaround) SRAMS
• Supports 8-bit and 16-bit Texas Instruments HPI specifications
• Multiplexed or non-multiplexed address / data busses for Intel/Motorola/HPI bus
cycles
• Supports even and odd parity generation and calculation for Intel/Motorola/Micron
ZBT modes
• Maximum clock input frequency of 80 MHz
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
®
IXP46X Product Line of Network Processors to external Expansion
®
, Synchronous Intel StrataFlash
®
Intel
®
Memory, Micron* Flow-Through ZBT,
®
Memory (16-bit and 32-bit only)
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
®
Developer's Manual
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