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USB 1.1 Device Controller—Intel
Processors
Packets are assembled into groups to produce transactions. Transactions fall into four
groups:
• Bulk
• Interrupt
Endpoint 0 is used only to communicate the control transactions that configure the
UDC. Endpoint 0s responsibilities include:
• Connection
• Bus enumeration
The UDC uses a dual-port memory to support FIFO operations. Each Bulk and
Isochronous Endpoint FIFO structure is double-buffered to enable the endpoint to
process one packet as it assembles another. The Intel XScale processor can fill and
empty the FIFOs. An interrupt is generated when a packet has been received.
Interrupts are also generated when the FIFO encounters a short packet or zero-length
packet. Endpoint 0 has a 16-entry-long, 8-bit-wide FIFO that can only be read or
written by the Intel XScale processor.
For endpoints 1-15, the UDC uses its dual-ported memory to hold data for a Bulk OUT
transaction while the transaction is checked for errors. If the Bulk OUT transaction data
is invalid, the UDC sends a NAK handshake to request the host to resend the data. The
software is not notified that the OUT data is invalid until the Bulk OUT data is received
and verified. If the host sends a NAK handshake in response to a Bulk IN data
transmission, the UDC resends the data. Because the FIFO maintains a copy of the
data, the software does not have to reload the data.
The external pins dedicated to the UDC interface are UDC+ and UDC-. The USB
protocol uses differential signalling between the two pins for half-duplex data
transmission. A 1.5-KΩ, pull-up resistor must be connected to the USB cable's D+
signal to pull the UDC+ pin high when it is not driven. Pulling the UDC+ pin high when
it is not driven allows the UDC to be a high-speed, 12-Mbps device and provides the
correct polarity for data transmission.
The serial bus uses differential signalling to transmit multiple states simultaneously.
These states are combined to produce transmit data and various bus conditions,
including:
• Idle
• End of Packet
• Reset
8.2
Device Configuration
The configuration of the Universal Serial Bus 1.1 Device Controller is shown in
Table
107.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network
• Control
• Isochronous
• Address assignment
• Disconnection
• Resume
• Disconnect
Intel
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
• Endpoint configuration
• Start of Packet
• Connect
Developer's Manual
279
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