Asynchronous Schedule State Machine Transition Actions; Typical Low- /Full-Speed Transaction Times - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
Table 173.

Asynchronous Schedule State Machine Transition Actions

Action
A
B
C
Async Sched Not Active
This is the initial state of the traversal state machine after a host controller reset. The
traversal state machine will not leave this state when the Asynchronous Schedule
Enable bit in the USBCMD register is a zero.
This state is entered from Async Sched Active or Async Sched Sleeping states
when the end-of-micro-frame event is detected.
Async Sched Active
This state is entered from the Async Sched Not Active state when the periodic
schedule is not active. It is also entered from the Async Sched Sleeping states when
the AsyncrhonousTraversalSleepTimer expires. On every transition into this state, the
host controller sets the Reclamation bit in the USBSTS register to a one.
While in this state, the host controller will continually traverse the asynchronous
schedule until either the end of micro-frame or an empty list condition is detected.
Async Sched Sleeping
The state is entered from the Async Sched Active state when a schedule empty
condition is detected. On entry to this state, the host controller sets the
AsynchronousTraversalSleepTimer to AsyncSchedSleepTime.
9.14.8.4.2 Example Derivation for AsyncSchedSleepTime
The derivation is based on analysis of what work the host controller could be doing
next. It assumes the host controller does not keep any state about what work is
possibly pending in the asynchronous schedule. The schedule could contain any mix of
the possible combinations of high- full- or low-speed control and bulk requests.
Table 174, "Typical Low- /Full-Speed Transaction Times" on page 437
some of the typical 'next transactions' that could be in the schedule, and the amount of
time (e.g. footprint, or wall clock) the transaction will take to complete.
Table 174. Typical Low- /Full-Speed Transaction Times (Sheet 1 of 2)
Transaction Attributes
Speed
Size
Type
Speed
Size
Type
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
On detection of the empty list, the host controller sets the
AsynchronousTraversalSleepTimer to AsyncSchedSleepTime.
When the AsynchronousTraversalSleepTimer expires, the host controller sets the
Reclamation bit in the USBSTS register to a one and moves the Nak Counter reload state
machine to WaitForListHead.
The host controller cancels the sleep timer (AsynchronousTraversalSleepTimer).
Footprint
(Time)
HS
11.9 µs
9.45 µs
512
Bulk
FS
~50 µs
64
Bulk
Action Description Label
Description
Maximum foot print for a worst-case, full-sized bulk data
transaction.
Maximum footprint for an approximate best-case, full-sized
bulk data transaction.
Approximate typical for full-sized bulk data. An 8-byte low-
speed is about 2x, or between 90 and 100 µs.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
summarizes
Developer's Manual
437