Glitch Suppression Logic - Intel IXP45X Developer's Manual

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Clear IDBR Receive Full bit to clear the interrupt.
Read IDBR data.
6. Read byte 2 with Nack (STOP is not set because STOP or Repeated START will be
decided on the byte read).
Write ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Set Ack/Nack
bit (Nack), Set Transfer Byte bit to initiate the access.
7. Wait for Buffer full interrupt.
Read status register: IDBR Receive Full (1), Unit Busy (1), R/W# bit (1), Ack/Nack
bit (1)
Clear IDBR Receive Full bit to clear the interrupt.
Read IDBR data.
There are now two options based on the byte read:
• Send a repeated START.
• Send a STOP only.
Here, a STOP abort is sent.
Note: Had a NACK not been sent, the next transaction must involve
8. Send STOP abort condition. (STOP with no data transfer.)
Write ICR: Set Master abort.
21.8

Glitch Suppression Logic

2
The I C Bus Interface Unit has built-in glitch suppression logic. Glitches will be
suppressed according to: 2 * (ICCR +1) * I
(30-ns period) I
50-ns glitch suppression specification. Note, that for glitch suppression to be within
specification, it is required that (ICCR + 1) * I
recommended that (ICCR + 1) * I
21.9 Reset Conditions
Software is responsible for ensuring the I
reset. Software is also responsible for ensuring the I
enabled after reset. When directed to reset, the I
condition.
When the Unit Reset bit in the ICR is set, only the I
network processors resets and the associated I
2
the I C unit with the ICR's unit reset, use the following guidelines:
1. In the ICR register, set the reset bit and clear the remainder of the register.
2. Clear the ISR register.
3. Clear reset in the ICR.
21.10 Register Definitions
The following registers are associated with the I
located within the peripheral memory-mapped address space of the IXP45X/IXP46X
network processors.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
another data byte read.
2
C clock, glitches of 60ns or less will be suppressed. This is within the
2
C clock period. For example, with a 33 MHz
2
C clock period > 25 ns. It is
2
C clock period = 30 ns.
2
C unit is not busy (ISR[3]) before asserting
2
C bus is idle when the unit is
2
C unit returns to its default reset
2
C unit of the IXP45X/IXP46X
2
C MMRs remain intact. When resetting
2
C Bus Interface Unit. They are all
August 2006
Order Number: 306262-004US