Udc Data Register 7; Udc Data Register 8 - Intel IXP45X Developer's Manual

Bits
31:8
7:0
8.5.37

UDC Data Register 7

Endpoint 7 is a double-buffered, bulk OUT endpoint that is 64 bytes deep. The UDC will
generate an interrupt request as soon as the EOP is received.
Since it is double-buffered, up to two packets of data may be ready. Via direct read
from the Intel XScale processor, the data can be removed from the UDC. If one packet
is being removed and the packet behind it has already been received, the UDC will
issue a NAK to the host the next time it sends an OUT packet to endpoint 7.
This NAK condition will remain in place until a full packet space is available in the UDC
at Endpoint 7.
Register Name:
0 x C800B680
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 7 Data Register
Description:
Access: Read
31
Bits
31:8
7:0
8.5.38

UDC Data Register 8

Endpoint 8 is a double-buffered, isochronous IN endpoint that is 256 bytes deep. Data
can be loaded via direct Intel XScale processor writes.
Because it-is double buffered, up to two packets of data may be loaded for
transmission.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
346
® ®
Intel IXP45X and Intel
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being loaded.
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being read.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDDR6
Description
UDDR7
0x00000000
Reset Hex Value:
Bits
UDDR7
Description
Controller
(UDDR7)
8 7
(8-Bit Data)
0 0 0 0 0 0 0
(UDDR8)
August 2006
Order Number: 306262-004US
0
0