Memory Attributes; Page (P) Attribute Bit; Cacheable (C), Bufferable (B), And Extension (X) Bits - Intel IXP45X Developer's Manual

Intel
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Intel StrongARM
which are 1 KByte in size. The reserved field in the first-level descriptor (encoding
0b11) is used as the fine page table base address. The exact bit fields and the format
of the first and second-level descriptors can be found in
page 175.
The attributes associated with a particular region of memory are configured in the
memory management page table and control the behavior of accesses to the
instruction cache, data cache, mini-data cache, and the write buffer. These attributes
are ignored when the MMU is disabled.
To allow compatibility with older system software, the new Intel XScale processor
attributes take advantage of encoding space in the descriptors that was formerly
reserved.
3.1.1

Memory Attributes

3.1.1.1

Page (P) Attribute Bit

The selection between address or data coherency is controlled by a software-
programmable P-Attribute bit in the Intel XScale processor's Memory Management Unit
(MMU) and the BYTE_SWAP_EN bit. The BYTE_SWAP_EN bit will be from Expansion Bus
Controller Configuration Register 1, bit 8. This bit will reset to 0.
The default endian-conversion method for the IXP45X/IXP46X network processors is
address coherency. This was selected for backward compatibility with the Intel
IXP425 Network Processor.
The BYTE_SWAP_EN bit is an enable bit that allows data coherency to be performed,
based on the P-Attribute bit.
• When the bit is 0, address coherency is always performed.
• When the bit is 1, the type of coherency performed is dependent on the P-Attribute
bit.
The P-Attribute bit is associated with each 1-Mbyte page. The P-Attribute bit is output
from the Intel XScale processor with any store or load access associated with that
page.
Note: The P-attribute feature allows software to control byte swapping per 1-Mbyte regions.
The P-attribute bit selectively enables or disables this byte swap feature. Future Intel
XScale processor products with L2 push cache will not support NPE byte-swapping per
1-Mbyte regions. Using the P-attribute bit to byte swap all of the NPE memory region
will allow compatible software code porting to future Intel XScale
P-attribute bit to byte-swap 1-Mbyte regions of the NPE memory will not allow
compatible software code porting to future Intel XScale technology.
3.1.1.2

Cacheable (C), Bufferable (B), and eXtension (X) Bits

3.1.1.2.1 Instruction Cache
When examining these bits in a descriptor, the Instruction Cache only utilizes the C bit.
If the C bit is clear, the Instruction Cache considers a code fetch from that memory to
be non-cacheable and will not fill a cache entry. If the C bit is set, then fetches from the
associated memory region will be cached.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
70
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
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MMU Version 5 Architecture introduces the support of tiny pages,
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Processor
"New Page Attributes" on
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Processor. Using the
August 2006
Order Number: 306262-004US