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USB 2.0 Host Controller—Intel
Table 140.
BURSTSIZE - Host Controller Embedded TT Async. Buffer Status
Field
(Reserved)
TXPBURST
RXPBURST
9.12.9
TXFILLTUNING
Address:
Default Value: 0x00020000
Attribute:
Size:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(Reserved)
The fields in this register control performance tuning associated with how the host
controller posts data to the TX latency FIFO before moving the data onto the USB bus.
The specific areas of performance include the how much data to post into the FIFO and
an estimate for how long that operation should take in the target system.
Definitions:
• T
= Standard packet overhead
0
• T
= Time to send data payload
1
• T
= Time to fetch packet into TX FIFO up to specified level.
ff
• T
= Total Packet Flight Time (send-only) packet
s
• T
= T
s
• T
= Total Packet Time (fetch and send) packet
p
• T
= T
p
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host
controller checks to ensure T
proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time
remaining the [micro]frame is < T
tried at a later time. Although this is not an error condition and the host controller will
eventually recover, a mark will be made the scheduler health counter to note the
occurrence of a "back-off" event. When a back-off event is detected, the partial packet
fetched may need to be discarded from the latency buffer to make room for periodic
traffic that will begin after the next SOF. Too many back-off events can waste
bandwidth and power on the system bus and thus should be minimized (not necessarily
eliminated). Back-offs can be minimized with use of the TSCHHEALTH (T
below.
9.12.10
CONFIGFLAG
Address:
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
These bits are reserved and their value has no effect on operation.
Programmable TX Burst Length. (Read/Write) Default is the constant
VUSB_HS_TX_BURST. This register represents the maximum length of a the burst in 32-
bit words while moving data from system memory to the USB bus.
Programmable RX Burst Length. (Read/Write) Default is the constant
VUSB_HS_RX_BURST. This register represents the maximum length of a the burst in 32-bit
words while moving data from the USB bus to system memory.
Base + 164h
Read/Write (Writes must be DWord Writes)
32 bits
TXFIFOTHRES
+ T
0
1
+ T
+ T
ff
0
1
remains before the end of the [micro]frame. If so it
p
Base + 180h
Description
(Rsvd)
TXSCHEALTH
then the packet attempt ceases and the packet is
s
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
1
TXSCHOH
) described
ff
Developer's Manual
0
381
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