Intel 21555 Manuals

Manuals and User Guides for Intel 21555. We have 1 Intel 21555 manual available for free PDF download: User Manual

Intel 21555 User Manual (198 pages)

Non-Transparent PCI-to-PCI Bridge

Brand: Intel | Category: Network Hardware | Size: 1 MB

Table of Contents
3
Preface
11
- Cautions and Notes
  12
- Data Units
  12
- Numbering
  12
- Signal Nomenclature
  13
- Signal Type Abbreviations
  13
- Register Abbreviations
  14
Introduction
15
- Comparing a 21555 to a Transparent PPB
  15
- 21555 Intelligent Controller Application
  16
- 21555 And PPB Feature Comparison
  17
- Architectural Overview
  18
  - Data Buffers
    18
  - Registers
    18
  - Control Logic
    18
- 21555 Microarchitecture
  19
- Special Applications
  20
  - Primary Bus VGA Support
    20
  - Secondary Bus VGA Support
    20
- Programming Notes
  20
  - Addressing
    20
- Decoded and Not Decoded Addresses
  20
  - Transaction Forwarding
    21
  - ROM Access
    21
Signal Descriptions
23
Address Decoding
33
Upstream Memory 2 Window Size
38
PCI Bus Transactions
49
Delayed Write Transaction Target Termination Returns
55
- Nonprefetchable Reads
  56
Delayed Read Transaction Target Termination Returns
56
Prefetch Boundaries
58
Transaction Ordering Rules
62
Initialization Requirements
65
- Power Management, Hot-Swap, and Reset Signals
  65
- Reset Behavior
  66
Reset Mechanisms
67
Power Management Actions
71
Clocking
77
Parallel ROM Interface
81
- Interface Signals
  81
PROM Interface Signals
82
Serial ROM Interface
91
Arbitration
97
Arbiter Control Register
100
Interrupt and Scratchpad Registers
101
- Primary and Secondary PCI Bus Interrupt Signals
  101
- Interrupt Support
  101
- Doorbell Interrupts
  103
- Scratchpad Registers
  103
Error Handling
105
- Error Signals
  105
- Parity Errors
  107
Parity Error Responses
107
- System Error (SERR#) Reporting
  110
JTAG Test Port
111
- JTAG Signals
  111
- Test Access Port Controller
  112
  - Initialization
    112
- Signal Trst_L States
  112
I2O Support
113
- Inbound Message Passing
  113
- Outbound Message Passing
  115
- Notes
  116
VPD Support
119
- Reading VPD Information
  119
- Writing VPD Information
  120
Register Cross Reference Table
121
- Configuration Registers
  122
List of Registers
121
- Register Summary
  121
Configuration Space Address Register
122
- Control and Status Registers
  126
CSR Address Map
126
- Address Decoding
  130
  - Primary and Secondary Address
    130
Primary CSR and Downstream Memory 0 Bar
130
Secondary CSR Memory Bars
131
Primary and Secondary CSR I/O Bars
132
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR
133
Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR
134
Upper 32 Bits Downstream Memory 3 Bar
135
Upstream Memory 2 Bar
135
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register
136
Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base Register
137
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers
138
Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers
139
- Configuration Transaction Generation Registers
  140
Upper 32 Bits Downstream Memory 3 Setup Register
140
Downstream and Upstream Configuration Address Registers
141
Downstream Configuration Data and Upstream Configuration Data Registers
142
Configuration Own Bits Register
142
Configuration CSR
143
Downstream I/O Address and Upstream I/O Address Registers
144
Downstream I/O Data and Upstream I/O Data Registers
145
I/O Own Bits Registers
145
Lookup Table Offset Register
146
- PCI Registers
  147
  - Configuration Registers
    147
Lookup Table Data Register
147
Upstream Memory 2 Lookup Table
147
Primary Interface Configuration Space Address Map
148
Secondary Interface Configuration Space Address Map
148
Vendor ID Register
148
Device ID Register
148
- Primary and Secondary Command Registers
  149
Primary and Secondary Status Registers
150
Revision ID (Rev ID) Register
151
Primary and Secondary Class Code Registers
152
Primary and Secondary Cache Line Size Registers
152
Primary Latency and Secondary Master Latency Timer Registers
153
Header Type Register
153
Bist Register
153
Subsystem Vendor ID Register
154
Subsystem ID Register
154
Enhanced Capabilities Pointer Register
154
Primary and Secondary Interrupt Line Registers
154
Primary and Secondary Interrupt Pin Registers
155
Primary and Secondary Minimum Grant Registers
155
- Device-Specific Control and Status Registers
  156
Primary and Secondary Maximum Latency Registers
155
Device-Specific Control and Status Address Map
156
Chip Control 0 Register
156
Chip Control 1 Register
160
Chip Status Register
162
Generic Own Bits Register
164
- I2O Registers
  165
I2O Outbound Post_List Status
165
I2O Outbound Post_List Interrupt Mask
165
I2O Inbound Post_List Status
165
I2O Inbound Post_List Interrupt Mask
166
I2O Inbound Queue
166
I2O Outbound Queue
166
I2O Inbound Free_List Head Pointer
167
I2O Inbound Post_List Tail Pointer
167
I2O Outbound Free_List Tail Pointer
167
I2O Outbound Post_List Head Pointer
167
I2O Inbound Post_List Counter
168
I2O Inbound Free_List Counter
168
I2O Outbound Post_List Counter
169
I2O Outbound Free_List Counter
169
- Interrupt Registers
  170
Chip Status CSR
170
Chip Set IRQ Mask Register
170
Chip Clear IRQ Mask Register
171
Upstream Page Boundary IRQ 0 Register
171
Upstream Page Boundary IRQ 1 Register
172
Upstream Page Boundary IRQ Mask 0 Register
172
Upstream Page Boundary IRQ Mask 1 Register
172
Primary Clear IRQ and Secondary Clear IRQ Registers
173
Primary Set IRQ and Secondary Set IRQ Registers
173
- Scratchpad 0 through Scratchpad 7 Registers
  174
- Scratchpad Registers
  174
Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers
174
Primary Set IRQ Mask and Secondary Set IRQ Mask Registers
174
- PROM Registers
  175
Primary Expansion ROM BAR
175
Primary Expansion ROM Setup Register
176
ROM Setup Register
177
ROM Data Register
177
ROM Address Register
178
ROM Control Register
178
- SROM Registers
  179
Mode Setting Configuration Register
179
Serial Preload Sequence
180
- Arbiter Control
  183
- Error Registers
  183
Primary SERR# Disable Register
184
- Init Registers
  185
Secondary SERR# Disable Register
184
Power Management ECP ID and Next Pointer Register
185
Power Management Capabilities Register
186
Power Management Control and Status Register
187
PMCSR Bridge Support Extensions
187
Power Management Data Register
188
Reset Control Register
188
- JTAG Registers
  190
JTAG Instruction Register Options
190
Bypass Register
191
- VPD Registers
  192
Boundary-Scan Register
191
Boundary Scan Order
191
Vital Product Data (VPD) ECP ID and Next Pointer Register
192
Vital Product Data (VPD) Address Register
193
VPD Data Register
193
Index
197

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