Intel IXF1104 Manuals

Manuals and User Guides for Intel IXF1104. We have 1 Intel IXF1104 manual available for free PDF download: Datasheet

Intel IXF1104 Datasheet

Intel IXF1104 Datasheet (231 pages)

4-Port Gigabit Ethernet Media Access Controller

Brand: Intel | Category: Network Hardware | Size: 3.34 MB

Table of Contents

Product Features
1
Table of Contents
3
0X00200000
13
Introduction

20
- What You will Find in this Document
  20
- Related Documents
  20
- Revision Date: 27-Oct
  20
General Description

21
- Block Diagram
  21
- Internal Architecture
  22
Ball Assignments and Ball List Tables

23
Ball Assignments and Signal Descriptions

37
Functional Descriptions

66
- Media Access Controller (MAC)
  66
  - Features for Fiber and Copper Mode
    67
    
    Automatic CRC Generation
    67
    
    Filtering of Receive Packets
    67
    
    Padding of Undersized Frames on Transmit
    67
    
    CRC Error Detection
    69
  - Flow Control
    69
- CRC Errored Packets Drop Enable Behavior
  69
  - Flow Control (Full-Duplex Operation)
    70
  - Packet Buffering FIFO
    71
  - Ethernet Frame Format
    71
  - PAUSE Frame Format
    72
  - Transmit Pause Control Interface
    74
- Valid Decodes for TXPAUSEADD[2:0]
  74
  - Mixed-Mode Operation
    75
    
    Configuration
    75
    
    Key Configuration Registers
    75
    
    Fiber Mode
    76
- Operational Mode Configuration Registers
  76
- Document Number
  76
  - Fiber Auto-Negotiation
    77
  - Document Number
    77
  - Determining if Link Is Established in Auto-Negotiation Mode
    77
  - Fiber Forced Mode
    77
  - Determination of Link Establishment in Forced Mode
    77
  - Copper Mode
    77
  - Speed
    78
  - Duplex
    78
  - Copper Auto-Negotiation
    78
  - Jumbo Packet Support
    78
    
    Loss-Less Flow Control
    79
    
    Rx Statistics
    79
    
    TX Statistics
    79
  - Packet Buffer Dimensions
    80
    
    TX and RX FIFO Operation
    80
  - RMON Statistics Support
    80
- RMON Additional Statistics
  81
  - Conventions
    82
  - Advantages
    83
- SPI3 Interface
  83
  - MPHY Operation
    84
    
    SPI3 RX Round Robin Data Transmission
    84
  - MPHY Logical Timing
    84
    
    Receive Timing
    85
    
    Transmit Timing
    85
  - MPHY Transmit Logical Timing
    85
  - MPHY Receive Logical Timing
    86
  - MPHY 32-Bit Interface
    86
    
    Clock Rates
    87
    
    Parity
    87
    
    SPHY Mode
    87
    
    Receive Timing (SPHY)
    88
    
    SPHY Logical Timing
    88
    
    Transmit Timing (SPHY)
    88
  - SPHY Transmit Logical Timing
    88
  - SPHY Receive Logical Timing
    89
  - SPHY Connection for Two Intel ® IXF1104 MAC Ports (8-Bit Interface)
    90
    
    SPI3 Flow Control
    91
  - Pre-Pending Function
    93
- Gigabit Media Independent Interface (GMII)
  93
- GMII Interface Signal Definitions
  95
- Reduced Gigabit Media Independent Interface (RGMII)
  96
  - Multiplexing of Data and Control
    96
  - RGMII Interface
    96
  - Timing Specifics
    97
  - TX_ER and RX_ER Coding
    97
- RGMII Signal Definitions
  97
  - TX_ER and RX_ER Coding Description
    97
  - RX_CTL Behavior
    98
    
    In-Band Status
    99
  - TX_CTL Behavior
    98
  - 10/100 Mbps Functionality
    99
- MDIO Control and Interface
  99
  - MDIO Address
    100
  - MDIO Register Descriptions
    100
  - Clear When Done
    100
  - MDC Generation
    100
    
    MDC High-Frequency Operation
    100
    
    MDC Low-Frequency Operation
    100
  - Management Frames
    101
  - Single MDI Command Operation
    101
  - MDI State Machine
    101
  - Management Frame Structure (Single-Frame Format)
    101
  - MDI State
    102
  - Autoscan Operation
    103
- Serdes Interface
  103
  - Features
    103
  - Functional Description
    103
    
    Document Number
    104
    
    Serdes Driver TX Power Levels
    104
    
    Transmitter Operational Overview
    104
    
    Transmitter Programmable Driver-Power Levels
    104
    
    Receiver Jitter Tolerance
    105
    
    Receiver Operational Overview
    105
    
    Selective Power-Down
    105
    
    Receive Jitter
    106
    
    Transmit Jitter
    106
  - Serdes Receiver Jitter Tolerance
    106
  - Optical Module Interface
    107
    
    Intel® IXF1104 MAC-Supported Optical Module Interface Signals
    107
    
    Functional Descriptions
    108
    
    High-Speed Serial Interface
    108
    
    Low-Speed Status Signaling Interface
    108
    
    I 2 C Control and Data Registers
    110
    
    I 2 C Read Operation
    110
    
    I²C Module Configuration Interface
    110
    
    I 2 C Write Operation
    111
  - C Random Read Transaction
    111
    
    I²C Protocol Specifics
    112
    
    Clock and Data Transitions
    113
    
    Port Protocol Operation
    113
  - Data Validity Timing
    113
  - Start and Stop Definition Timing
    113
  - Acknowledge Timing
    114
  - LED Interface
    115
    
    Modes of Operation
    115
  - Random Read
    115
    
    LED Interface Signal Description
    116
    
    Mode 0: Detailed Operation
    116
  - Mode 0 Timing
    116
    
    Mode 1: Detailed Operation
    117
- Mode 0 Clock Cycle to Data Bit Relationship
  117
  - Power-On, Reset, Initialization
    118
  - LED DATA Decodes
    118
  - Mode 1 Timing
    118
- Mode 1 Clock Cycle to Data Bit Relationship
  118
  - LED Signaling Behavior
    119
- LED_DATA# Decodes
  119
- LED Behavior (Fiber Mode)
  119
  - CPU Interface
    120
- LED Behavior (Copper Mode)
  120
  - Functional Description
    121
    
    Read Access
    121
    
    Write Access
    121
  - Read Timing Diagram - Asynchronous Interface
    121
    
    CPU Timing Parameters
    122
    
    Endian
    122
  - Write Timing Diagram - Asynchronous Interface
    122
  - TAP Interface (JTAG)
    123
    
    TAP State Machine
    123
- Byte Swapper Behavior
  123
  - Instruction Register and Supported Instructions
    124
- Instruction Register Description
  124
  - ID Register
    125
  - Boundary Scan Register
    125
  - Bypass Register
    125
  - Loopback Modes
    125
    
    SPI3 Interface Loopback
    125
    
    Line Side Interface Loopback
    126
  - SPI3 Interface Loopback Path
    126
  - Clocks
    127
    
    System Interface Reference Clocks
    127
  - Line Side Interface Loopback Path
    127
    
    Clk125
    128
    
    MDC Clock
    128
    
    RGMII Clocks
    128
    
    SPI3 Receive and Transmit Clocks
    128
    
    I 2 C Clock
    129
    
    JTAG Clock
    129
    
    LED Clock
    129
Contents

130
Applications

130
- Change Port Mode Initialization Sequence
  130
- Disable and Enable Port Sequences
  131
  - Disable Port Sequence
    131
  - Enable Port Sequence
    131
Electrical Specifications

132
- Absolute Maximum Ratings
  132
  - DC Specifications
    133
- Recommended Operating Conditions
  133
- Serdes Transmit Characteristics
  134
  - DC Specifications
    134
  - RGMII Electrical Characteristics
    135
  - Undershoot / Overshoot Specifications
    135
- Serdes Receive Characteristics
  135
- Undershoot / Overshoot Limits
  135
- RGMII Power
  136
  - SPI3 AC Timing Specifications
    137
    
    Receive Interface Timing
    137
  - SPI3 Receive Interface Timing
    137
- SPI3 Receive Interface Signal Parameters
  138
  - Transmit Interface Timing
    139
  - SPI3 Transmit Interface Timing
    139
- SPI3 Transmit Interface Signal Parameters
  140
  - RGMII AC Timing Specification
    141
Contents

141
- RGMII Interface Timing
  141
  - RGMII Interface Timing Parameters
    141
  - GMII AC Timing Specification
    142
    
    1000 Base-T Operation
    142
    
    1000 BASE-T Transmit Interface
    142
- 1000BASE-T Transmit Interface Timing
  142
- GMII 1000BASE-T Transmit Signal Parameters
  142
  - 1000BASE-T Receive Interface
    143
- 1000BASE-T Receive Interface Timing
  143
- GMII 1000BASE-T Receive Signal Parameters
  143
  - Serdes AC Timing Specification
    144
- Serdes Timing Diagram
  144
- Serdes Timing Parameters
  144
  - MDIO AC Timing Specification
    145
    
    MDC High-Speed Operation Timing
    145
    
    MDC Low-Speed Operation Timing
    145
    
    MDIO AC Timing
    146
- MDIO Write Timing Diagram
  146
- MDIO Read Timing Diagram
  146
- MDIO Timing Parameters
  146
  - Optical Module and I 2 C AC Timing Specification
    147
    
    I 2 C Interface Timing
    147
- Bus Timing Diagram
  147
- Write Cycle Diagram
  147
  - CPU AC Timing Specification
    149
    
    CPU Interface Read Cycle AC Timing
    149
    
    CPU Interface Write Cycle AC Timing
    149
- CPU Interface Write Cycle AC Signal Parameters
  150
  - Transmit Pause Control AC Timing Specification
    151
- Pause Control Interface Timing
  151
  - JTAG AC Timing Specification
    152
- JTAG AC Timing
  152
  - JTAG AC Timing Parameters
    152
  - System AC Timing Specification
    153
- System Reset AC Timing
  153
  - System Reset AC Timing Parameters
    153
  - LED AC Timing Specification
    154
- LED AC Interface Timing
  154
- LED Interface AC Timing Parameters
  154
Register Set

155
Contents

164
Mechanical Specifications

224
- Overview
  224
  - Features
    224
  - Package Specifics
    224
  - Package Information
    225
    
    CBGA Package Diagrams
    225
- CBGA Package Diagram
  225
- CBGA Package Side View Diagram
  226
  - Flip Chip-Plastic Ball Grid Array Package Diagram
    227
- FC-PBGA Package (Top and Bottom Views)
  227
- FC-PBGA Mechanical Specifications
  228
  - Top Label Marking Example
    229
Product Ordering Information

230
- Product Information
  230
- Ordering Information – Sample
  231

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