Mvip, Interleaved Mapping Of A T1 Frame To An E1 Frame - Intel IXP45X Developer's Manual

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HSS Coprocessor—Intel IXP45X and Intel
• Frame sync simultaneous with first data nibble – set TX frame offset and RX frame
offset due to HSS logic, different values due to external device can be
accommodated.
• Select use of input/output TX/RX frame syncs.
• Select use of input/output clock, and clock speed.
• Select negative/positive clock for generating/sampling frame in transmit/receive.
• Select negative/positive clock for generating/sampling data in transmit/receive.
• Frame sync active level (high/low).
• MSb/LSb-first ordering for transmit and receive.
• Data polarity, maintain or invert.
• Select not to use FBit in the frame.
• Select level for idle timeslots on transmit and unused bit in 56k timeslots.
• Select buffer size.
• Set interlace mode (byte/frame)
• Set lookup tables.
The clocks must be capable of running at 1.544 MHz, 2,048 MHz, 4.096 and 8.192 MHz
for MVIP mode.
The following three sections describe the three ways in which the protocol can operate.
The TX and RX are not explicitly described below, as the RX side of the protocol is
identical to the TX side of the protocol.
13.5.4.1 2.048-Mbps Backplane
The clock rate for this form of T1 is 2.048Mbps as opposed to the usual T1 rate of 1.544
Mbps. The data rate remains at 1.544Mbps, meaning that certain timeslots within the
frame carry no data and thus are discarded by the HSS (unassigned timeslots,
configured by the look up tables).
Figure 178. MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame
2.048
MHz clock
Frame pulse
5 6 7 0 1 2
Bits
Timeslot 23 X 0 1 2 X 3 4 5 X 6 7 8 X 9 10 11 X 12 13 14 X 15 16 17 X 18 19 20 X 21 22 23
Unused timeslots
August 2006
Reference Number: 306262-004US
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IXP46X Product Line of Network Processors
3 4 5 6 7 FBit X X X X X X X 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
Figure 178 below illustrates the point.
ignored
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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B4249-01
Developer's Manual
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