Utopia Level 2 Mphy Transmit Polling - Intel IXP45X Developer's Manual

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UTOPIA Level 2—Intel IXP45X and Intel
check (CRC) residue register to produce the value for the next HEC CRC residue. The
HEC is generated new for every cell transmitted and has no dependencies on previous
cells transmitted.
The HEC residue may be inserted directly into the data stream being transmitted over
the UTOPIA Level 2 interface or, optionally, the HEC residue may be exclusive-ORed
with hexadecimal 0x55 — to generate a COSET value, before being inserted into the
data stream.
The HEC value is available one clock period after the last byte of the header information
is transmitted. Therefore, a complete stream of cell data (H0, H1, H2, H3, HEC, D0, D1,
...) can be transmitted in successive clock cycles without interruption to the data
stream.
When the Transmit HEC (TxHEC) configuration bit is enabled, the UTOPIA transmit
interface will always insert an extra byte (valid HEC) into the cell being transmitted. In
normal operation (TxHEC is enabled), the UTOPIA 2 Coprocessor Transmit Module will
expect 52 bytes from the Transmit FIFO and the Transmit Module will insert a valid HEC
field into the data stream.
Figure 33
assumptions are made for the figure:
• There are eight active physical interfaces connected, named A through H, that map
to logical address 0 through 7.
• Physical Interface A is the currently selected physical interface for clock cycles 0
through18.
• Notice on clock 8 that the result from Physical Interface G is that Physical Interface
G is ready to receive a cell. The UTP_OP_FCI signal flags that a full cell can be sent
to Physical Interface G by the Physical Interface asserting the UTP_OP_FCI to logic
1 one clock after Physical Interface G has been polled.
• On clock 17, the final Physical Interface polled is the Physical Interface that is
currently selected. This polling is irrelevant to the Physical Interface that was polled
previously prior to this location.
• Notice on clock cycles 19 and 20 that Physical Interface G is selected as the next
Physical Interface that the IXP45X/IXP46X network processors will transmit data
to.
Figure 33.

UTOPIA Level 2 MPHY Transmit Polling

0
UTP_OP_CLK
UTP_OP_ADDR (4:0)
X
UTP_OP_FCI
(a.k.a. -TX_CLAV )
UTP_OP_FCO
(a.k.a. -TX_ENB_N )
35
UTP_OP_DATA (7:0)
UTP_OP_SOC
August 2006
Reference Number: 306262-004US
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IXP46X Product Line of Network Processors
shows the transmission of a cell in multiple-PHY (MPHY) mode. The following
1 2 3 4 5 6 7 8
D X E X F X G X
36 37 38 39 40 41 42 43
9 10 11 12 13 14 15 16
H X A X B X C X
44 45 46 47 48 49 50 51
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
17 18 19 20 21 22 23 24
A X G X D X E X
52 53 1 2 3 4 5
Developer's Manual
25 26
F X
6 7
B4325 -02
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