Ahb Doorbell Register - Intel IXP45X Developer's Manual

Register
Bits Name
31:2 Upper 8 PCI address bits for AHB accesses that target the first 16MB PCI
PCIbase0
4 memory partition.
23:1 Upper 8 PCI address bits for AHB accesses that target the second 16MB
PCIbase1
6 PCI memory partition.
Upper 8 PCI address bits for AHB accesses that target the third 16MB PCI
15:8 PCIbase2
memory partition.
Upper 8 PCI address bits for AHB accesses that target the fourth 16MB PCI
7:0 PCIbase3
memory partition.
10.5.3.15

AHB Doorbell Register

Register Name:
Block
0xC00000
Base Address:
This register is write-1-to-set from PCI and write-1-to-clear from
AHB. The PCI device writes a 1 to a bit or pattern of bits to
generate the interrupt. The AHB agent reads the register and
Register Description:
writes 1(s) to clear the bit(s) and deassert the interrupt. If the DBT
(Doorbell Test) bit is set in the pci_csr register, all bits become
read/write from the AHB bus.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
PCI generated doorbell interrupt to an AHB agent. Normally read/write-1-
31:0 ADB to-set from PCI and read/write-1-to-clear from AHB. Read/write from the
AHB side if Doorbell Test mode is enabled by setting pci_csr.DBT to a 1.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
568
® ®
Intel IXP45X and Intel
Description
Offset Address
ADB
Description
IXP46X Product Line of Network Processors—PCI Controller
pci_pcimembase
pci_ahbdoorbell
0x38
pci_ahbdoorbell
Reset PCI AHB
Value Access Access
0x00 RO
0x00 RO
0x00 RO
0x00 RO
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset PCI AHB
Value Access Access
RW1C
0x0000 (RW if
RW1S
0000 pci_csr.
DBT=1)
August 2006
Order Number: 306262-004US
RW
RW
RW
RW
0