Intel IXP45X Developer's Manual page 29

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Contents-Intel IXP45X and Intel
184 UART Block Diagram............................................................................................... 752
185 GPIO Block Diagram ............................................................................................... 777
186 Interrupt Controller Block Diagram ........................................................................... 806
187 Operating System Timer Block Diagram .................................................................... 818
188 Block Diagram of TSync Circuit ................................................................................ 831
189 Time Stamp Reference Point.................................................................................... 832
2
190 I C Bus Interface Unit Block Diagram........................................................................ 876
2
191 I C Bus Configuration Example ................................................................................ 877
192 START and STOP Conditions .................................................................................... 880
193 START and STOP Condition Events ........................................................................... 881
194 Data Format of First Byte in Master Transaction ......................................................... 883
195 Acknowledge on the I
196 Clock Synchronization During the Arbitration Procedure............................................... 885
197 Arbitration Procedure of Two Masters........................................................................ 885
198 Master-Receiver Read from Slave-Transmitter............................................................ 888
199 Master-Receiver Read from Slave-Transmitter / Repeated Start /
Master-Transmitter Write to Slave-Receiver ............................................................... 889
200 A Complete Data Transfer ....................................................................................... 889
201 Master-Transmitter Write to Slave-Receiver ............................................................... 891
202 Master-Receiver Read to Slave-Transmitter ............................................................... 891
203 Master-Receiver Read to Slave-Transmitter, Repeated START,
Master-Transmitter Write to Slave-Receiver ............................................................... 891
204 General Call Address .............................................................................................. 892
205 AHB-PKE Bridge Block Diagram ................................................................................ 908
206 Exponentiation Acceleration Unit: Block Diagram ........................................................ 914
207 AHB Queue Manager .............................................................................................. 927
208 Representative Logical Diagram of a Queue ............................................................... 931
209 NPE Error Handling Illustration................................................................................. 953
Tables
1 List of Acronyms ...................................................................................................... 39
2 Register Legend....................................................................................................... 43
3 Supported DDRI Memory Configurations ..................................................................... 54
4 GPIO Alternate Function Table ................................................................................... 57
5 Data Cache and Buffer Behavior When X = 0 ............................................................... 71
6 Data Cache and Buffer Behavior When X = 1 ............................................................... 72
7 Memory Operations that Impose a Fence..................................................................... 72
8 Valid MMU & Data/Mini-Data Cache Combinations......................................................... 73
9 MRC/MCR Format..................................................................................................... 97
10 LDC/STC Format when Accessing CP14 ....................................................................... 97
11 CP15 Registers ........................................................................................................ 98
12 ID Register ............................................................................................................. 99
13 Cache Type Register................................................................................................. 99
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14 Intel StrongARM
15 Auxiliary Control Register ........................................................................................ 101
16 Translation Table Base Register ............................................................................... 102
17 Domain Access Control Register ............................................................................... 102
18 Fault Status Register .............................................................................................. 103
19 Fault Address Register ............................................................................................ 103
20 Cache Functions..................................................................................................... 104
21 TLB Functions ........................................................................................................ 105
22 Cache Lock-Down Functions .................................................................................... 105
23 Data Cache Lock Register........................................................................................ 105
24 TLB Lockdown Functions ......................................................................................... 106
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
2
C Bus.................................................................................... 884
*
Control Register ......................................................................... 100
Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
29