T1 Rx Frame Using External Frame Pulse - Intel IXP45X Developer's Manual

In Figure
be received is padded with 7 other bits (zeros) and placed into the HSS Receive FIFO.
Figure 172. T1 RX Frame Using External Frame Pulse
hss_rx_clock
hss_rx_frame
hss_rx_data
By using the IxHssAcc API, the following settings should be considered when
configuring HSS interface for T1 operation:
• Frame size 193 bits (for T1).
• Frame sync simultaneous with FBit – TX frame offset and RX frame offset should be
set due to HSS logic, different values due to external device can be accommodated.
• Select use of input/output TX/RX frame syncs.
• Select use of input/output clock, and clock speed.
• Select negative/positive clock for generating/sampling frame in transmit/receive.
• Select negative/positive clock for generating/sampling data in transmit/receive.
• Frame sync active level (high/low).
• MSb/LSb-first ordering for transmit and receive.
• Data polarity, maintain or invert.
• Select to use FBit (not data for T1) at frame start.
• Select value for idle timeslots on transmit and unused bit in 56k timeslots.
• Select buffer size.
• Configure lookup tables.
13.5.2 E1
This is a high-speed serial stream operating at 2.048 MHz. The stream is composed of
frames of which there are 8000 a second. Each frame consists of 32 slots, each slot is a
byte in size. As there are 32 slots per frame, E1 can carry 32 channels. There are no
frame bits in this protocol.
Figure 173,
frame sync (level) and a positive edge clock for generating or sampling data. The HSS
clock and frame pulse can be programmed to be either HSS outputs or HSS inputs. An
offset can be can programmed indicating when the TX frame is to be transmitted. The
polarity of the received data and the level of the frame can also be programmed using
the IxHssAcc API.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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Intel IXP45X and Intel
172, as stated in Section 13.3, "Theory of Operation" on page
FBit data1 data2
Figure 174, and Figure 175
IXP46X Product Line of Network Processors—HSS Coprocessor
data 191 data 192
illustrate a typical E1 frame with an active high
726, the FBit to
FBit data1
B4240-02
August 2006
Reference Number: 004US