Eight-Word Inbound Write With Ex_Slave_Cs_N Deassertion - Intel IXP45X Developer's Manual

decided to start another NOP cycle in cycle 3. If EX_WAIT_N was asserted in cycle 2,
the external master cannot start a NOP in cycle 3. It must wait until EX_WAIT_N is
sampled deasserted.
12.4.5.6

Eight-Word Inbound Write with EX_SLAVE_CS_N Deassertion

Figure 155. Eight-Word Inbound Write with EX_SLAVE_CS_N Deassertion
- 0 - - 1 -
EX_CLK
EX_ IXPCS_N
EX_ ADDR
ADDR0
EX_RD_N
EX_WR_N
EX_BE_N
EX_ BURST
EX_ WAIT_N
EX_ DATA
EX_ PARITY
STATE
IDLE NOP
The above timing diagram shows an external master choosing to deassert
EX_SLAVE_CS_N in the middle of an 8-word write. The external master can deassert
EX_SLAVE_CS_N anytime after EX_WAIT_N is sampled deasserted. It can also deassert
it between any of the 8 words being transferred. In the above diagram, the master
deasserted EX_SLAVE_CS_N in cycle 3. When resuming the burst, the master must
increment EX_ADDR[4:2] by 0x1. Once the transfer for EX_ADDR[4:2] = 0x7 is
complete, the Expansion bus controller will transfer all 8 words to the AHB. The
Expansion bus controller will never assert EX_WAIT_N on word 2-8 of the burst.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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Intel IXP45X and Intel
- 3 - - 4 - - 5 -
- 2 -
ADDR1 ADDR2
DATA0 DATA1
PAR0 PAR1
DATA0 DATA0 IDLE DATA1
IXP46X Product Line of Network Processors—Expansion Bus
- 6 - - 7 - - 8 -
ADDR3 ADDR4 ADDR5
DATA2 DATA3 DATA4
PAR2 PAR3 PAR4
DATA2 DATA3 DATA4
Controller
- 9 - - 10 - - 11 - - 12 -
ADDR6 ADDR7
DATA5 DATA6 DATA7
PAR5 PAR6 PAR7
DATA5 DATA6 DATA7 IDLE
B4443-01
August 2006
Order Number: 306262-004US