Ddri Sdram Commands; Ddri Sdram Initialization - Intel IXP45X Developer's Manual

11.2.2.7

DDRI SDRAM Commands

The MCU issues specific commands to the DDRI SDRAM devices by encoding them on
the DDRI_CS_N[1:0], DDRI_RAS_N, DDRI_CAS_N, and DDRI_WE_N inputs.
lists all of the DDRI SDRAM commands understood by DDRI SDRAM devices. The MCU
supports a subset of these commands.
Table 211. DDRI SDRAM Commands
1,2
Command DDRI_
CS_N[1:0
]
NOP 0
Mode Register Set 0
Row Activate 0
Read 0
Read w/ Auto-
0
Precharge
Write 0
Write w/ Auto-
0
Precharge
Precharge 0
Precharge All 0
Auto-Refresh 0
Self-Refresh 0
Power Down X
Stop 0
1. This table copied from New DRAM Technologies by Steven Przybylski.
2. Shaded boxes indicate commands not supported by IXP45X/IXP46X network processors. They are included for completeness.
3. During a Mode Register Set command, DDRI_BA[1:0] = 00
Extended Mode Register, all others are served.
DDRI SDRAM commands are synchronous to the clock so the MCU sets up the above
conditions prior to the DDRI_CK[2:0] rising edge.
11.2.2.8

DDRI SDRAM Initialization

Since DDRI SDRAM devices contain a controller within the device, the MCU must
initialize them specifically. Upon the deassertion of RESET_IN_N, software initializes the
DDRI SDRAM devices with the sequence described below and illustrated in
1. The MCU applies the clock DDRI_CK[2:0] at power up along with system power
(clock frequency unknown).
2. The MCU must stabilize DDRI_CK[2:0] within 100 µs after power stabilizes.
3. The MCU holds the following control inputs inactive:
DDRI_RAS_N, DDRI_CAS_N, DDRI_WE_N, DDRI_CS_N[1:0]
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Conditions
DDRI_ DDRI_
RAS_N CAS_N
1 1
0 0
0 1
1 0
1 0
1 0
1 0
0 1
0 1
0 0
0 0
X X
1 1
IXP46X Product Line of Network Processors—Memory Controller
DDRI_
Other
WE_N
1
DDRI_BA[0] = Sel
0
DDRI_BA[1] = 0
1 DDRI_BA[1:0] = Leaf
DDRI_BA[1:0] = Leaf
1
DDRI_MA[10] = 0
DDRI_BA[1:0] = Leaf
1
DDRI_MA[10] = 1
DDRI_BA[1:0] = Leaf
0
DDRI_MA[10] = 0
DDRI_BA[1:0] = Leaf
0
DDRI_MA[10] = 1
DDRI_BA[1:0] = Leaf
0
DDRI_MA[10] = 0
0 DDRI_MA[10] = 1
1
1 CKE = 0
X CKE = 0
0
selects the Mode Register, DDRI_BA[1:0] = 01
2
Table 211
Comments
No Operation
3
Load the (Extended) Mode
Register from DDRI_MA[13:0]
Activate a row specified on
DDRI_MA[13:0]
Column burst read
Column address on
DDRI_MA[13:0]
Column burst read with row
precharge at the end of the
transfer
Column burst write
Column address on
DDRI_MA[13:0]
Column burst write with row
precharge at the end of the
transfer
Precharge a single leaf
Precharge all leaves
Refresh both banks from on-chip
refresh counter
Refresh autonomously while CKE
= 0
Power down if both banks
precharged when CKE = 0
Interrupt a read or write burst.
selects the
2
Figure
August 2006
Order Number: 306262-004US
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