Expansion Bus Inbound Timing Diagrams; Back-To-Back 1-Word Inbound Write With Ex_Slave_Cs_N Deasserted; Back-To-Back 1-Word Writes Without Deasserting Ex_Slave_Cs_N - Intel IXP45X Developer's Manual

12.4.5

Expansion Bus Inbound Timing Diagrams

The next several timing diagrams show several representations of some of the
supported inbound bus protocol. The Expansion bus controller is not limited to the
possibilities of the timing diagrams shown. Timing diagrams with varying combinations
of NOPS, Master waits, back-to-back transfers are all supported as long as the rules
that are described in
12.4.5.1 Back-to-Back 1-Word Inbound Write with EX_SLAVE_CS_N
Deasserted
Figure 150
waits. In the second write the master chose to insert a NOP in cycle 3. In the third
write, the Expansion bus controller is busy and asserts EX_WAIT_N in cycle 9. The
Expansion bus controller will assert EX_WAIT_N one cycle after the assertion of
EX_SLAVE_CS_N and EX_WR_N if its not ready to transfer data. If EX_WAIT_N is
asserted, the master cannot end the burst until EX_WAIT_N is deasserted. For 1-word
writes, the Expansion bus controller only transfers the data that is presented on the
cycle that EX_SLAVE_CS_N is deasserted. In the timing diagram the master chose to
tri-state EX_DATA/EX_PARITY in cycles 3 and 7, however this is not mandatory and can
be driven.
Figure 150. Back-to-Back 1-Word Inbound Write with EX_SLAVE_CS_N Deasserted
- 0 - - 1 -
EX_ CLK
EX_ IXPCS_N
EX_ ADDR
ADDR0
EX_RD_N
EX_WR_N
EX_BE_N
BE0
EX_ BURST
EX_ WAIT_N
EX_ DATA
EX_ PARITY
STATE
IDLE DATA0
12.4.5.2 Back-to-Back 1-Word Writes without Deasserting
EX_SLAVE_CS_N
Figure 151
external master must deassert EX_WR_N between the writes and the Expansion bus
controller will assert EX_WAIT_N once EX_WR_N is re-asserted in cycle 4. When the
Expansion bus controller observes EX_WR_N deasserting in cycle 2 and 6, it captures
the data.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
690
®
Intel IXP45X and Intel
Section 12.4.2, "Inbound Transfers" on page 681
shows three 1-word writes. The first transaction is a 1-word write with no
- 2 - - 3 - - 4 - - 5 -
ADDR1
BEy
DATA0
PAR0
DATA0 IDLE NOP DATA1
shows multiple 1-word writes without deasserting EX_SLAVE_CS_N. The
®
IXP46X Product Line of Network Processors—Expansion Bus
- 6 - - 7 - - 8 - - 9 -
DATA1
PAR1
DATA1 IDLE NOP WAIT
are followed.
- 10 - - 11 - - 12 - - 13 -
ADDR2
BE2
DATA2
PAR2
DATA2 DATA2
August 2006
Order Number: 306262-004US
Controller
- 14 -
IDLE
B4438-01