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®
Intel XScale
Processor—Intel
Table 9.
MRC/MCR Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
31:28
23:21
20
19:16
15:12
11:8
7:5
3:0
The format of LDC and STC for CP14 is shown in
programming notes in the ARM* Architecture Reference Manual. Note that access to
CP15 with LDC and STC will cause an undefined exception.
LDC and STC transfer a single 32-bit word between a coprocessor register and
memory. These instructions do not allow the programmer to specify values for
opcode_1, opcode_2, or Rm; those fields implicitly contain zero, which means the
performance monitoring registers are not accessible.
Table 10.
LDC/STC Format when Accessing CP14 (Sheet 1 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
31:28
24:23,21
22
20
August 2006
Order Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
1
1
1
0 opcode_1 n
Description
®
*
cond - Intel
StrongARM
condition codes
opcode_1 - Reserved
n - Read or write coprocessor register
0 = MCR
1 = MRC
CRn - specifies which coprocessor register
Rd - General-Purpose Register, R0..R15
cp_num - coprocessor number
opcode_2 - Function bits
CRm - Function bits
1
1
0
P
U N W L
Description
®
*
cond - Intel
StrongARM
condition codes
P, U, W - specifies 1 of 3 addressing modes
identified by addressing mode 5 in the ARM*
Architecture Reference Manual.
N - should be 0 for CP14 coprocessors. Setting
this bit to 1 has will have an undefined effect.
L - Load or Store
0 = STC
1 = LDC
Intel
CRn
Rd
cp_num
-
Should be programmed to zero for future
compatibility
-
-
-
Intel XScale
coprocessors:
0b1111 = CP15
0b1110 = CP14
0x0000 = CP0
Note:
Mappings are implementation defined
for all coprocessors below CP14 and
above CP0. Access to unimplemented
coprocessors (as defined by the
cpConfig bus) cause exceptions.
This field should be programmed to zero for
future compatibility unless a value has been
specified in the command.
This field should be programmed to zero for
future compatibility unless a value has been
specified in the command.
Table
10. LDC and STC follow the
Rn
CRd
cp_num
-
-
-
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
opcode_2 1
CRm
Notes
®
Processor defines three
8
7
6
5
4
3
2
8_bit_word_offset
Notes
Developer's Manual
1
0
1
0
97
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