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USB 2.0 Host Controller—Intel
9.12.12
USBMODE
Address:
Default Value: 0x00000000
00000003h (host mode)
Attribute:
Size:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Table 142.
USBMODE - USB Device Mode
Field
(Reserved)
SDIS
(Reserved)
ES
CM[1:0]
9.13
Host Data Structures
This section defines the interface data structures used to communicate control, status,
and data between HCD (software) and the Enhanced Host Controller (hardware). The
data structure definitions in this chapter support a 32-bit memory buffer address
space. The interface consists of a Periodic Schedule, Periodic Frame List, Asynchronous
Schedule, Isochronous Transaction Descriptors, Split-transaction Isochronous Transfer
Descriptors, Queue Heads, and Queue Element Transfer Descriptors.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
Base + 1A8h
R/WO, Read Only
32 bits
(Reserved)
These bits are reserved and should be zero.
Stream Disable Mode. (0 – Inactive [default]; 1 – Active)
Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated
for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire
packet. Enabling stream disable also has the effect of ensuring that the TX latency is filled to
capacity before the packet is launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See
TXFILLTUNING to characterize the adjustments needed for the scheduler when using this
feature.
Note:
The use of this feature substantially limits of the overall USB performance that can be
achieved.
(Reserved)
Endian Select – Read/Write. This bit can change the byte alignment of the transfer buffers
to match the host microprocessor. The bit fields in the microprocessor interface and the data
structures are unaffected by the value of this bit because they are based upon the 32-bit word.
Bit
Meaning
0
little-endian [Default]
1
big-endian
Controller Mode – R/WO. Controller mode is defaulted to the proper mode for host only
implementations. For those designs that contain host capability, the controller will default to an
idle state and will need to be initialized to the desired operating mode after reset. For host
controllers, this register can only be written once after reset. If it is necessary to switch modes,
software must reset the controller by writing to the RESET bit in the USBCMD register before
reprogramming this register.
Bit Meaning
00 Idle [Default for combination host]
01 (Reserved)
10 (Reserved)
11 Host Controller [Default for host only controller]
Intel
Description
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
1
ES
Developer's Manual
0
CM
387
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