Intel IXP45X Developer's Manual page 805

Interrupt Controller—Intel
Table 261. Intel XScale
Interrupt
Bit
Int32
Int33
Int34
Int35
Int36
Int37
Int38
Int39
Int40
Int41
Int42
Int43
Int44
Int45
Int46
Int47
Int48
Int49
Int50
Int51
Int52
Int53
Int54
Int55
Int56
Int57
Int58
Int59
Int60
Int61
In62
Int63
† Priorities of Interrupts 0 through 7 are programmable, 8 through 63 are fixed. Priority 0 is
highest priority, 63 is lowest.
17.2 Feature List
• 64 Supported Interrupts
• Priority encoded servicing of interrupts
• Ability to program the order of the 8 highest priority interrupts.
• Handles pclk- and hclk-generated interrupts
August 2006
Reference Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
®
Processor Interrupt Mapping (Sheet 2 of 2)
Default
Source
†
Priority
32 USB Host
33 I2C
34 SSP
35 TSync
36 EAU
37 SHA
38 Reserved
39 Reserved
40 Reserved
41 Reserved
42 Reserved
43 Reserved
44 Reserved
45 Reserved
46 Reserved
47 Reserved
48 Reserved
49 Reserved
50 Reserved
51 Reserved
52 Reserved
53 Reserved
54 Reserved
55 Reserved
56 Reserved
57 Reserved
58 SWCP
59 Reserved
60 QM
61 MCU
62 EXP
63 Reserved
Description
USB Host Interrupt
I2C Interrupt
SSP Interrupt
TimeSync Interrupt
EAU Done Interrupt
SHA Hashing Done Interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SWCP Parity Error
Reserved
Queue Manager Parity Error
Multi-Bit ECC Error
Expansion Bus Parity Error
Reserved
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
805