Typical Refresh Frequency Register Values; Error Correction And Detection - Intel IXP45X Developer's Manual

• After T
another refresh cycle.
It is recommended that the RFR is programmed with the value to achieve 7.8 us,
though some DDRI SDRAM devices may provide for the ability to refresh at a period of
15.6 us. See
is based on the frequency of the DDRI SDRAM and
typical values.
Table 212.

Typical Refresh Frequency Register Values

The longest possible internal bus transaction is writing a 32-byte burst where each data
cycle results in a read-modify-write due to partial writes. See
Generation for Partial Writes"
transactions where each of the transaction are page misses and partial writes.
The MCU uses a 2-bit counter to queue refresh cycles. If another refresh cycle is
queued when a current refresh cycle completes, the MCU services the queued refresh
cycle before servicing any internal bus requests. If the counter exceeds three (which
should never happen), the counter does NOT roll over and three refreshes will be
serviced when the MCU is available.
11.2.3

Error Correction and Detection

The MCU is capable of correcting any single bit errors and detecting any double bit
errors in the's DDRI SDRAM memory subsystem for the IXP45X/IXP46X network
processors. ECC enhances the reliability of a memory subsystem by correcting single
bit errors caused by electrical noise or occasional alpha particle hits on the DDRI
SDRAM devices.
Similar to parity, which simply detects single bit errors, error correction requires an
additional 8-bit code word for the 32-bit datum. This means that a memory must have
the additional 8-bit error correction code DDRI_CB[7:0] per 32-bit datum
DDRI_DQ[31:0] resulting in a 40-bit wide memory subsystem. During DDRI SDRAM
read cycles, the DDRI SDRAM Control Block detects single-bit errors and corrects the
data prior to returning the data to the respective memory transaction queue. DDRI
SDRAM write cycles generate the ECC and sends it with the data to the memories.
In 32-bit wide memory, the IXP45X/IXP46X network processors will zero extend the
32-bit datum to a 64-bit datum in order to generate, check and correct ECC. This
means that a 32-bit datum memory with ECC will result in a 40-bit wide memory since
an 8-bit error correction code is still required.
The ECC algorithm for the IXP45X/IXP46X network processors uses the H-matrix/G-
Matrix method used by the Pentium
non-zero syndrome and indicates which bit was incorrect for single-bit errors.
Scrubbing is the process of correcting an error in the memory array. The chance of an
unrecoverable multi-bit error increases if the software does not correct a single-bit
error in the array. For the IXP45X/IXP46X network processors, scrubbing is handled by
software. If error reporting is enabled, the MCU logs the error type in ELOG0 or ELOG1
and the address in ECAR0 or ECAR1 when an error occurs.
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cycles, the DDRI SDRAM Control Block can service a new transaction or
rfc
Section 11.6.14, "Refresh Frequency Register RFR"
DDRI Speed
266 MHz
for details. The longest possible CMTQ tenure is 16
IXP46X Product Line of Network Processors—Memory Controller
Table 212
7.8 μs Value
0410H
®
Pro Processor (Figure
for details. The value
can provides for these two
15.6 μs Value
0820H
Section 11.2.3.2, "ECC
122). The H-matrix reads a
August 2006
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