Port Routing And Control; Example Usb 2.0 Host Controller Port Routing Block Diagram - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
9.14.2

Port Routing and Control

A USB 2.0 Host controller is comprised of one high-speed host controller, which
implements the EHCI programming interface and 0 to N USB 1.1 companion host
controllers. Companion host controllers (cHCs) may be implementations of either
Universal or Open host controller specifications. This configuration is used to deliver the
required full USB 2.0-defined port capability; e.g. Low-, Full-, and High-speed
capability for every port.
Diagram" on page 411
its relationship to the high-speed and companion host controllers within a USB 2.0 Host
controller.
Figure 52.

Example USB 2.0 Host Controller Port Routing Block Diagram

Port Routing
There is one transceiver per physical port and each host controller module has its own
port status and control registers. The EHCI controller has port status and control
registers for every port. Each companion host controller has only the port control and
status registers it is required to operate. Each transceiver can be controlled by either
the EHCI host controller or one companion host controller. Routing logic lies between
the transceiver and the port status and control registers.
The port routing logic is controlled from signals originating in the EHCI host controller.
The EHCI host controller has a global routing policy control field and per-port ownership
control fields. The Configured Flag (CF) bit (defined in
page 380) is the global routing policy control. At power-on or reset, the default routing
policy is to the companion controllers (if they exist). If the system does not include a
driver for the EHCI host controller and the host controller includes Companion
Controllers, then the ports will still work in Full- and Low-speed mode (assuming the
system includes a driver for the companion controllers). In general, when the EHCI
owns the ports, the companion host controllers' port registers do not see a connect
indication from the transceiver. Similarly, when a companion host controller owns a
port, the EHCI controller's port registers do not see a connect indication from the
transceiver. The details on the rules for the port routing logic are described in the
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
"Example USB 2.0 Host Controller Port Routing Block
illustrates a simple block diagram of the port routing logic and
USB 2.0 Host Controller
Companion
USB 1.1 HC
Data
Logic
Transceiver
Port 1
1
Port Reg
Section 9.12.8, "BURSTSIZE" on
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
High-Speed
(ehci) HC
Data Port Reg
Port
Owner
B4470-01
Developer's Manual
411