Expansion Bus Controller Response To Errors - Intel IXP45X Developer's Manual

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Error Handling—Intel IXP45X and Intel
28.2.3

Expansion Bus Controller Response to Errors

When the Expansion Bus Controller receives an AHB error response, it will return data
to the requesting master on the Expansion Bus, but will assert invalid parity on all
bytes to let that master know that the data it is receiving is not valid.
28.2.4 Intel XScale
When the Intel XScale
MCU interface, it transition to its fault handler. A second such error can irretrievably
lose the program counter, causing unpredictable system results. This is the inherent
nature of the ARM* architecture which is not altered by the IXP45X/IXP46X network
processors.
All other errors reported by the system will be seen by the host processor via interrupt
signals to the interrupt controller. As a result of such information, the host processor
may attempt to clean up the system on its own, rather than reboot.
If the Intel XScale
errors in internal memories or AHB errors to the AHB coprocessor, the IXP45X/IXP46X
network processors may attempt to reset the afflicted NPE, reload its software, and
restart. To ensure that the North AHB bus is not rendered unusable, a handshake signal
between the AHB coprocessor and the reset mechanism in the Expansion Bus Controller
will be implemented to ensure that the AHB coprocessor is idle before allowing reset to
propagate to that unit.
An important functional note is that parity errors are possible as a result of reads to the
DMEM or IMEM from the APB. In this event, the only indication of an error condition to
the source of the request will be an interrupt to the Intel XScale
this, error handling is only supported for accesses initiated by the Intel XScale
Processor. Other masters, such as the PCI Controller or Expansion Bus Controller, are
not supported.
28.2.5 AHB-AHB Bridge Response to Errors
When the AHB-AHB Bridge receives an AHB error on the South AHB, it will respond with
an AHB error on the North AHB to the originating master.
28.3 Multiple Error Conditions
It is possible, even likely, that multiple error conditions might occur within the response
period of the Intel XScale
DMEM may result not only in an indication of their condition, but the AHB Coprocessor
will error as a result of the NPE beginning its shutdown process. Similarly, an error in
the Queue Manager may result not only in an indication of error to the Interrupt
Controller, but a resulting error returned to the NPE which is accessing the Queue
Manager may result in an error condition in the NPE.
No attempt to validate multiple error scenarios is implemented as a function in
hardware. It is the responsibility of the system software to determine an appropriate
response to a multiple error scenario.
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Processor Response to Errors
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Processor receives an error on the AHB Bus or on its private
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Processor receives indication that an NPE has locked up due to
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Processor. As an example, parity errors in the IMEM or
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Intel IXP45X and Intel
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Processor. Due to
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IXP46X Product Line of Network Processors
Developer's Manual
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