Performance Monitoring; Overview; Performance Monitoring Registers - Intel IXP45X Developer's Manual

®
Intel XScale Processor—Intel
3.7

Performance Monitoring

This section describes the performance monitoring facility of the IXP45X/IXP46X
network processors. The events that are monitored can provide performance
information for compiler writers, system application developers and software
programmers.
3.7.1

Overview

The hardware for the IXP45X/IXP46X network processors provides four 32-bit
performance counters that allow four unique events to be monitored simultaneously. In
addition, the IXP45X/IXP46X network processors implement a 32-bit clock counter that
can be used in conjunction with the performance counters; its main purpose is to count
the number of core clock cycles which is useful in measuring total execution time.
The IXP45X/IXP46X network processors can monitor either occurrence events or
duration events. When counting occurrence events, a counter is incremented each time
a specified event takes place and when measuring duration, a counter counts the
number of processor clocks that occur while a specified condition is true. If any of the
five counters overflow, an interrupt request will occur if it is enabled. Each counter has
its own interrupt request enable. The counters continue to monitor events even after
an overflow occurs, until disabled by software.
Each of these counters can be programmed to monitor any one of various events.
To further augment performance monitoring, the IXP45X/IXP46X network processors'
clock counter can be used to measure the executing time of an application. This
information combined with a duration event can feedback a percentage of time the
event occurred with respect to overall execution time.
All of the performance monitoring registers are accessible through Coprocessor 14
(CP14). Refer to
MCR coprocessor instructions. Access is allowed in privileged mode only. Note that
these registers can't be access with LDC or STC coprocessor instructions.
Table 55.

Performance Monitoring Registers

(PMNC) Performance Monitor Control
Register
(CCNT) Clock Counter Register
(INTEN) Interrupt Enable Register
(FLAG) Overflow Flag Register
(EVTSEL) Event Selection Register
(PMN0) Performance Count Register 0
(PMN1) Performance Count Register 1
(PMN2) Performance Count Register 2
(PMN3) Performance Count Register 3
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Table 29 for more details on accessing these registers with MRC and
Description
Intel
CRn CRm
Register Register
# #
Read: MRC p14, 0, Rd, c0, c1, 0
0b0000 0b0001
Write: MCR p14, 0, Rd, c0, c1, 0
Read: MRC p14, 0, Rd, c1, c1, 0
0b0001 0b0001
Write: MCR p14, 0, Rd, c1, c1, 0
Read: MRC p14, 0, Rd, c4, c1, 0
0b0100 0b0001
Write: MCR p14, 0, Rd, c4, c1, 0
Read: MRC p14, 0, Rd, c5, c1, 0
0b0101 0b0001
Write: MCR p14, 0, Rd, c5, c1, 0
Read: MRC p14, 0, Rd, c8, c1, 0
0b1000 0b0001
Write: MCR p14, 0, Rd, c8, c1, 0
Read: MRC p14, 0, Rd, c0, c2, 0
0b0000 0b0010
Write: MCR p14, 0, Rd, c0, c2, 0
Read: MRC p14, 0, Rd, c1, c2, 0
0b0001 0b0010
Write: MCR p14, 0, Rd, c1, c2, 0
Read: MRC p14, 0, Rd, c2, c2, 0
0b0010 0b0010
Write: MCR p14, 0, Rd, c2, c2, 0
Read: MRC p14, 0, Rd, c3, c2, 0
0b0011 0b0010
Write: MCR p14, 0, Rd, c3, c2, 0
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Instruction
Developer's Manual
157