Frx Frame Sync Example (Presuming Zero Offset); Underflow/Overflow/Unexpected Frame Pulse - Intel IXP45X Developer's Manual

Figure 169. FRX Frame Sync Example (Presuming Zero Offset)
hss_rx_clock
hss_rx_frame
hss_rx_data
13.3.4

Underflow/Overflow/Unexpected Frame Pulse

Underflow occurs if the HSS attempts to read from a FIFO which has not been filled by
the NPE Core.
If this occurs in a HSS core, then all transmission in that core in that direction is halted
and an error condition is indicated to the NPE Core. Once the NPE Core has
acknowledged that error condition (hss_error condition signal), the HSS core will wait
until the beginning of the next frame to request for data. That data will be transmitted
on the start of the following frame. In the case where the 2 HSS cores simultaneously
underflow, HSS core 0 always gets priority.
Within each core can be multiple FIFOs, 5-2 FIFOs (4 hdlc+2voice to 1 hdlc + 1 voice).
In the case where a number of these FIFOs underflow in around the same time, the
first FIFO to underflow will be the one indicated to the NPE Core. When the NPE Core
reads the error register, all FIFO errors and the FIFOs themselves in the HSS core for
that direction are cleared. Upon reading the error register, the tx condition signals from
the HSS core are cleared. The conditions signals will go high again when data is needed
for transmission.
If synchronization is attained but the NPE Core withholds sending data to the HSS TX
FIFOs for many frames, the HSS will not indicate that as an error and the TX condition
flag will remain asserted.
Overflow occurs if the HSS attempts to write to a FIFO that has not been emptied by
the NPE Core. If this occurs, then all reception in that HSS core is halted until the NPE
Core acknowledges this condition by reading the error register. Once this has occurred,
the HSS will start filling the RX FIFOs at the start of the next frame (offset
compensated).
In the case where the two HSS cores overflow simultaneously then HSS core 0 will
always be given priority. Once serviced, HSS core 1 is then allowed to indicate its
overflow error to the NPE Core.
Within each core can be multiple FIFOS, 5-2 FIFOs (4 hdlc+2voice to 1 hdlc + 1 voice).
In the case where a number of these FIFOs overflow in around the same time, the first
FIFO to overflow will be the one indicated to the NPE Core. When the NPE Core reads
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Correct interval
Data from here is processed
IXP46X Product Line of Network Processors—HSS Coprocessor
data data data
B4237-02
August 2006
Reference Number: 004US