Ahb Queue Manager - Intel IXP45X Developer's Manual

AHB Queue Manager (AQM)—Intel
Processors
• Programmable queue size supported (queues may be configured for 16, 32, 64 or
128 word buffer)
• Maintains empty (E), nearly empty (NE), nearly full (NF), and full (F) status flags
on each of the queues 0-63
• Programmable queue watermarks for assessing NE and NF queue status flags
• Provides status flag information, E, NE, F and NF, for queues 0-31 to the NPEs via a
common Flag Bus
• Provides Underflow and Overflow Status Flags for each of the queues 0-31
• Programmable event status enable for queues 32-63
• Two Intel XScale processor interrupts, one for queues 0-31 and one for queues 32-
63
• Individual interrupt enables for each queue
• Programmable interrupt source for each of the queues 0-31 as the assertion or de-
assertion of 1 of 4 status flags, E, NE, NF or F
• NE status flag used as the interrupt source for each of the queues 32-63
• Provides read/write access to all queues, queue pointers, status flags, configuration
registers, interrupt registers and SRAM via the AHB
• SRAM core computes and checks parity and provides error registers
27.3 Block Diagram
Figure 207. AHB Queue Manager
Figure 207
bus present(s) a unified flag bus to each of the NPE CCPs (Condition Coprocessors) that
are to be connected. AQM instantiations are driven from the AHB bus and all operations
August 2006
Reference Number: 306262-004US
®
IXP45X and Intel
Queue
Control
Queue
Config/Status
Buffer
Registers
SRAM

AHB Queue Manager

shows a high level block diagram of the AQM and its connections. The flag
®
IXP46X Product Line of Network
AHB
AHB
Slave
FLAG BUS
EVENT BUS
INT
Intel XScale
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
NPE
M
®
Core
B4305-01
Developer's Manual
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