Start And Stop Conditions; Start Condition; No Start Or Stop Condition - Intel IXP45X Developer's Manual

Intel
Figure 192. START and STOP Conditions
SDA
SCL
21.4.3.1

START Condition

The START condition (bits 1:0 of the ICR set to 2'b01) initiates a master transaction or
repeated START. Software must load the target slave address and the R/W# bit in the
IDBR (see
ICR bit. The START and the IDBR contents are transmitted on the I
Transfer Byte bit is set. The I
requested or enters master-receive mode when a read is requested. For a repeated
start (a change in read or write or a change in the target slave address), the IDBR
contains the updated target slave address and the R/W# bit. A repeated start enables
multiple transfers to different slaves without giving up the bus.
The START condition is not cleared by the I
initiating a START, the I
See "Arbitration" on page 884
circumstances.
21.4.3.2

No START or STOP Condition

No START or STOP condition (bits 1:0 of the ICR set to 2'b00) is used in master-
transmit mode while the processor is transmitting multiple data bytes (see
Software writes the data byte, sets the IDBR Transmit Empty bit in the ISR (and
interrupt when enabled), and clears the Transfer Byte bit in the ICR. The software then
writes a new byte to the IDBR and sets the Transfer Byte ICR bit, which initiates the
new byte transmission. This continues until the software sets the START or STOP bit.
The START and STOP bits in the ICR are not automatically cleared by the I
the transmission of a START, STOP or repeated START.
After each byte transfer (including the Ack/Nack bit) the I
(inserting wait states) until the Transfer Byte bit in the ICR is set. This action notifies
2
the I C unit to release the SCL line and allow the next information transfer to proceed.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
880
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
Start Condition
"I2C Data Buffer Register - IDBR" on page
2
C bus stays in master-transmit mode when a write is
2
C unit may re-attempt the START when the bus becomes free.
for details on how the I
902) before setting the START
2
C unit. When arbitration is lost while
2
C unit functions under those
2
C unit holds the SCL line low
Order Number: 306262-004US
Stop Condition
B4257-01
2
C bus when the ICR
Figure 192).
2
C unit after
August 2006