Dbgrx Data Register - Intel IXP45X Developer's Manual

®
Intel XScale Processor—Intel
Figure 18.

DBGRX Data Register

TDI
cleared by
RX Write Logic
3.6.11.6.3 DBG.RR
The debugger uses DBG.RR as part of the synchronization that occurs between the
debugger and debug handler for accessing RX. This bit contains the value of
TXRXCTRL[31] after a Capture_DR. The debug handler automatically sets
TXRXCTRL[31] by doing a write to RX.
The debugger polls DBG.RR to determine when the handler has read the previous data
from RX.
The debugger sets TXRXCTRL[31] by setting the DBG.V bit.
3.6.11.6.4 DBG.V
The debugger sets this bit to indicate the data scanned into DBG_SR[34:3] is valid data
to write to RX. DBG.V is an input to the RX Write Logic and is also cleared by the RX
Write Logic.
When this bit is set, the data scanned into the DBG_SR will be written to RX following
an Update_DR. If DBG.V is not set and the debugger does an Update_DR, RX will be
unchanged.
This bit does not affect the actions of DBG.FLUSH or DBG.D.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
0
DBG_SR
35 34
DBG_REG
34 33
TCK
RX TXRXCTRL[31]
3
2
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
0 1
Capture_DR
TDO
2 1 0
DBG.RR
Update_DR
1 0
DBG.FLUSH
DBG.D
DBG.RX
DBG.V
B4344-01
Developer's Manual
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