Ecc Checking - Intel IXP45X Developer's Manual

11.2.3.3

ECC Checking

If enabled, the ECC logic uses the following ECC read algorithm. This algorithm corrects
the data before it is driven onto the internal bus.
The ECC algorithm for a read transaction is:
Read 64/32-bit data and 8-bit ECC (For the IXP45X/IXP46X network processors,32 bit
read data is zero extended to 64 bits)
Compute the syndrome by passing the 64-bit data through the G-Matrix and XORing
the 8-bit result with the 8-bit ECC
if the syndrome <> 0 {ECC Error}
Look up in H-matrix to determine error type
Register the address where the error occurred
if error is correctable {single bit}
else {uncorrectable}
When the MCU reads the ECC code from the memory subsystem, it is compared
(XORed) with an ECC that the MCU generates from the data read from the memory.
The result is called the syndrome.
syndrome for DDRI SDRAM read cycles.
Table 213. Syndrome Decoding
Error Type
None
Single-Bit
Multi-Bit
Figure 121
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if single-bit error correction is enabled
Correct data
Send corrected data to internal bus
if single bit error reporting is enabled
Interrupt core for software scrubbing
if the read cycle is not part of a RMW cycle {read}
Target-Abort the Internal Bus read transaction.
else {write requiring RMW}
Merge the new data portion with the read data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
if multi-bit error reporting is enabled
Interrupt the core for uncorrectable error
The syndrome is 0000 0000.
Use the H-Matrix in Figure 122
If the Syndrome does not match an 8-bit value in the H-matrix, the error is uncorrectable.
shows how the data flows through the ECC hardware for a read transaction.
IXP46X Product Line of Network Processors—Memory Controller
Table 213 shows how the MCU decodes the
Symptom
to determine which bit the MCU will invert to fix the error.
August 2006
Order Number: 306262-004US