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USB 1.1 Device Controller—Intel
Processors
Register Name:
0x C800B048
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 14 Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.17
UDC Endpoint 15 Control/Status Register
The UDC Endpoint 15 Control Status Register contains six bits that are used to operate
endpoint 15, an Interrupt IN endpoint.
8.5.17.1
Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and
UDCCS15[TSP] is not set.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Receive short packet (read only).
RSP
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
RNE
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
(Reserved)
Receive overflow (read/write 1 to clear).
ROF
1 = Isochronous data packets are being dropped from the host because the
receiver is full.
Receive packet complete (read/write 1 to clear).
RPC
0 = Error/status bits invalid.
1= Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS
0 = Receive FIFO has less than one data packet.
1 = Receive FIFO has one or more data packets.
Intel
UDCCS14
0x00000000
Reset Hex Value:
UDCCS14
Description
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
(UDCCS15)
Developer's Manual
0
0
325
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