Udc Endpoint 10 Control/Status Register - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Bits
3
2
1
0
8.5.12

UDC Endpoint 10 Control/Status Register

The UDC Endpoint 10 Control Status Register contains six bits that are used to operate
Endpoint 10, an Interrupt IN endpoint.
8.5.12.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and
UDCCS10[TSP] is not set.
8.5.12.2 Transmit Packet Complete (TPC)
The transmit packet complete bit is be set by the UDC when an entire packet is sent to
the host. When this bit is set, the IR10 bit in the appropriate UDC status/interrupt
register is set if transmit interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 10 Control/
Status Register. The UDCCS10[TPC] bit is cleared by writing a 1 to it. This clears the
interrupt source for the IR10 bit in the appropriate UDC status/interrupt register, but
the IR10 bit must also be cleared.
The UDC issues NAK handshakes to all IN tokens if this bit is set and the buffer is not
triggered by writing 8 bytes or setting UDCCS10[TSP].
8.5.12.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit's read value is 0.
8.5.12.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, NAK handshakes are sent to the host.
UDCCS10[TUR] does not generate an interrupt and is for status only. UDCCS10[TUR] is
cleared by writing a 1 to it.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Register
Name
(Reserved)
Receive overflow (read/write 1 to clear).
ROF
1 = Isochronous data packets are being dropped from the host because the
receiver is full.
Receive packet complete (read/write 1 to clear).
RPC 0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS 0 = Receive FIFO has less than one data packet.
1 = Receive FIFO has one or more data packets.
Intel
UDCCS9
(Sheet 2 of 2)
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(UDCCS10)
Developer's Manual
315