Instruction Breakpoints; Data Breakpoints; Instruction Breakpoint Address And Control Register (Ibcrx); Data Breakpoint Register (Dbrx) - Intel IXP45X Developer's Manual

Intel
In this section Modified Virtual Address (MVA) refers to the virtual address ORed with
the PID. Refer to
The processor does not OR the PID with the specified breakpoint address prior to doing
address comparison. This must be done by the programmer and written to the
breakpoint register as the MVA. This applies to data and instruction breakpoints.
3.6.6.1

Instruction Breakpoints

The Debug architecture defines two instruction breakpoint registers (IBCR0 and
IBCR1). The format of these registers is shown in Table 37., Instruction Breakpoint
Address and Control Register (IBCRx). In Intel
contain a word aligned MVA to break on. In Thumb mode, the upper 31 bits contain a
half-word aligned MVA to break on. In both modes, bit 0 enables and disables that
instruction breakpoint register. Enabling instruction breakpoints while debug is globally
disabled (DCSR.GE=0) may result in unpredictable behavior.
Table 37.

Instruction Breakpoint Address and Control Register (IBCRx)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable address, disabled
Bits
31:1
0
An instruction breakpoint will generate a debug exception before the instruction at the
address specified in the ICBR executes. When an instruction breakpoint occurs, the
processor sets the DBCR.moe bits to 0b001.
Software must disable the breakpoint before exiting the handler. This allows the break-
pointed instruction to execute after the exception is handled.
Single step execution is accomplished using the instruction breakpoint registers and
must be completely handled in software (either on the host or by the debug handler).
3.6.6.2

Data Breakpoints

The debug architecture of the IXP45X/IXP46X network processors defines two data
breakpoint registers (DBR0, DBR1). The format of the registers is shown in
Table 38.

Data Breakpoint Register (DBRx)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
118
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
"Register 13: Process ID" on page 106
Access
Read / Write
Read / Write
Access
Read / Write
for more details on the PID.
® *
StrongARM mode, the upper 30 bits
IBCRx
Description
Instruction Breakpoint MVA
® *
in Intel StrongARM mode, IBCRx[1] is ignored
IBCRx Enable (E) -
0 = Breakpoint disabled
1 = Breakpoint enabled
DBRx
Description
DBR0: Data Breakpoint MVA
DBR1:
Data Address Mask OR
Data Breakpoint MVA
®
Processor
8 7 6 5 4 3 2 1
Table 38.
8 7 6 5 4 3 2 1
August 2006
Order Number: 306262-004US
0
E
0