Serial Clock Rate (Scr) - Intel IXP45X Developer's Manual

Synchronous Serial Port—Intel
When the SSE bit is cleared during active operation, the SSP is disabled immediately,
causing the current frame being transmitted to be terminated. Clearing SSE resets the
SSP's FIFOs. However the SSP's control and status registers are not reset. The user
must ensure these registers are properly reconfigured before re-enabling the SSP.
20.5.1.5

Serial Clock Rate (SCR)

The 8-bit serial clock rate (SCR) bit-field is used to select the baud, or bit rate, of the
SSP. A total of 256 different bit rates can be selected, ranging from a minimum of
7.2 Kbps to a maximum of 1.8432 Mbps. The serial clock generator uses the
3.6864 MHz clock produced by the on-chip PLL divided by a fixed value of 2, and then
divided by the programmable SCR value (0 to 255) plus 1 to generate the serial clock
(SSP_SCLK). The resultant clock is driven on the SSP_SCLK pin and is used by the
SSP's transmit logic to drive data on the SSP_TXD pin, and to latch data on the
SSP_RXD pin. Depending on the frame format selected, each transmitted bit is driven
on either the rising or falling edge of SSP_SCLK, and is sampled on the opposite clock
edge.
The following bit table presents the bit locations corresponding to the five different
control bit fields within SSP control register 0. Note that the SSE bit is the only control
bit that is reset to a known state, to ensure the SSP is disabled following a reset. The
reset state of all other control bits is unknown and must be initialized before enabling
the SSP.
Register Name:
Block
0xC801_20
Base Address:
SSC Control Register 0
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
Register
Bit Name
31:16 (Reserved) (Reserved)
Serial Clock Rate Selection
15:08 SCR Value (0 to 255) used to generate transmission rate of SSP.
Bit rate = 3.6864x10
Synchronous Serial Port Enable bit.
7 SSE
0 = SSP operation disabled
1 = SSP operation enabled
External clock select bit.
6 ECS
0 = On-chip clock used to produce the SSP's serial clock (SSP_SCLK).
1 = SSP_EXTCLK is used to create the SSP's SSP_SCLK.
This field specifies the Frame Format.
00 - Motorola* Serial Peripheral Interface (SPI)
5:4 FRF 01 - Texas Instruments* Synchronous Serial Protocol (SSP)
10 - National Microwire*
11 - Reserved, undefined operation
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Offset Address
Description
6
/ (2 x (SCR + 1)) where SCR is a decimal integer
Intel
SSCR0
0x00
SCR
SSCR0 (Sheet 1 of 2)
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
0x0000_0000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
FRF SRS
Reset
Access
Value
0x0000 RV
X RW
0x0000 RW
0x0000 RW
0x0000 RW
Developer's Manual
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