Occurrence Events - Intel IXP45X Developer's Manual

Intel
• Overflow detection and interrupt
• Previous Master and Slave information
The event counters are used to monitor events across different interfaces of the
processor. The counters do nothing special to the events, only count the number of
cycles that the event is "TRUE". What makes an event a specific kind of performance
event is the logic which decodes operations from the monitored buses and creates
event streams to present to the event selection mux.
Unlike previous versions of the PMU, there are no "modes" or really any meaningful
difference between duration and occurrence events. There are only events and each
event has its description which defines what parameter is being measured. Some
events are defined as occurrence events and some are defined as a duration event, but
the implementation or programming of the PMU does not distinguish between any of
the cases. From the software and implementation perspective, all events are uniform
once they are presented to the selection mux. An occurrence event occurs only once
per occurrence and back-to-back events represent two occurrences. A duration event is
active the entire time the event is "TRUE." Back-to-back events may either represent
two disconnected events, back-to-back, or may represent consecutive cycles of the
same event. Occurrence events have the semantics of a count whereas duration events
have the semantics of time.
16.3.1 Programmable Event Counters
There are eight general-purpose, 27-bit wide Programmable Event Counters (PECx).
The reason for the size of the counter is to provide a count period of approximately one
second at 133 MHz. Each counter may be programmed to increment on detection of a
rising edge or continuously with a high level on the selected input signal. If any counter
generates an overflow, a flag is set and an interrupt sent to the interrupt controller. The
flag is cleared on a write to the PMU status register. The counters are reset whenever a
new mode is selected, (i.e., North, South or DRAM). Mode HALT (i.e. PMR set to
disabled) causes all counters to halt allowing the same time snap-shot to be read
across all counters.
The event that is being monitored by a counter is dependent on the ESR contents.
There is an eight bit field per counter which selects the event being presented to each
counter. In this way up to eight events may be selected for monitoring. There is some
redundancy between counter events to allow as many useful combinations to be
monitored as possible (see
The programmable event counters provide real-time monitoring capability. They are
memory mapped and may be read directly. All counters are reset and started whenever
a value is written to the ESR and the mode is not HALT.
16.3.2

Occurrence Events

An occurrence event causes the counter to increase by one each time the event occurs.
Table 254
IXP46X network processors. Note that the PMU monitors two AHB buses, the north and
south. The logic performing the monitoring does not distinguish between the two
buses, and the only effect that multiple buses has is to increase the number of events.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring
Table 260
presents the various occurrence events that are monitored on the IXP45X/
for combinations).
Unit (PMU)
August 2006
Order Number: 306262-004US