Register 9: Cache Lock Down; Tlb Functions; Cache Lock-Down Functions; Data Cache Lock Register - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
This register should be accessed as write-only. Reads from this register, as with an
MRC, have an undefined effect.
Table 21.

TLB Functions

Invalidate I&D TLB
Invalidate I TLB
Invalidate I TLB entry
Invalidate D TLB
Invalidate D TLB entry
3.5.1.10

Register 9: Cache Lock Down

Register 9 is used for locking down entries into the instruction cache and data cache.
(The protocol for locking down entries can be found in
Table 22
cache. The entry to lock in the instruction cache is specified by the virtual address in
Rd. The data cache locking mechanism follows a different procedure than the
instruction cache. The data cache is placed in lock down mode such that all subsequent
fills to the data cache result in that line being locked in, as controlled by
Lock/unlock operations on a disabled cache have an undefined effect.
Read and write access is allowed to the data cache lock register bit[0]. All other
accesses to register 9 should be write-only; reads, as with an MRC, have an undefined
effect.
Table 22.

Cache Lock-Down Functions

Fetch and Lock I cache line
Unlock Instruction cache
Read data cache lock register
Write data cache lock register
Unlock Data Cache
Table 23.

Data Cache Lock Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:1
0
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
Function opcode_2
0b000
0b000
0b001
0b000
0b001
shows the command for locking down entries in the instruction and data
Function opcode_2
0b000
0b001
0b000
0b000
0b001
Access
Read-unpredictable / Write-as-Zero
Read / Write
CRm Data
0b0111 Ignored
0b0101 Ignored
0b0101 MVA
0b0110 Ignored
0b0110 MVA
Chapter 3.0, "Data
CRm Data
0b0001 MVA
0b0001 Ignored
Read lock mode
0b0010
value
Set/Clear lock
0b0010
mode
0b0010 Ignored
Reserved
Data Cache Lock Mode (L)
0 = No locking occurs
1 = Any fill into the data cache while this bit is set gets
locked in
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Instruction
MCR p15, 0, Rd, c8, c7, 0
MCR p15, 0, Rd, c8, c5, 0
MCR p15, 0, Rd, c8, c5, 1
MCR p15, 0, Rd, c8, c6, 0
MCR p15, 0, Rd, c8, c6, 1
Cache".)
Table 23.
Instruction
MCR p15, 0, Rd, c9, c1, 0
MCR p15, 0, Rd, c9, c1, 1
MRC p15, 0, Rd, c9, c2, 0
MCR p15, 0, Rd, c9, c2, 0
MCR p15, 0, Rd, c9, c2, 1
8 7 6 5 4 3 2
Description
Developer's Manual
1 0
L
105