Register 8: Tlb Operations; Cache Functions - Intel IXP45X Developer's Manual

Intel
Disabling/enabling a cache has no effect on contents of the cache: valid data stays
valid, locked items remain locked. All operations defined in
whether the cache is enabled or disabled.
Since the Clean DCache Line function reads from the data cache, it is capable of
generating a parity fault. The other operations will not generate parity faults.
Table 20.

Cache Functions

Invalidate I&D cache & BTB
Invalidate I cache & BTB
Invalidate I cache line
Invalidate D cache
Invalidate D cache line
Clean D cache line
Drain Write (& Fill) Buffer
Invalidate Branch Target Buffer
Allocate Line in the Data Cache
The line-allocate command allocates a tag into the data cache specified by bits [31:5]
of Rd. If a valid dirty line (with a different MVA) already exists at this location it will be
evicted. The 32 bytes of data associated with the newly allocated line are not initialized
and therefore will generate unpredictable results if read.
Line allocate command may be used for cleaning the entire data cache on a context
switch and also when reconfiguring portions of the data cache as data RAM. In both
cases, Rd is a virtual address that maps to some non-existent physical memory. When
creating data RAM, software must initialize the data RAM before read accesses can
occur. Specific uses of these commands can be found in
Other items to note about the line-allocate command are:
• It forces all pending memory operations to complete.
• Bits [31:5] of Rd is used to specific the virtual address of the line to be allocated
into the data cache.
• If the targeted cache line is already resident, this command has no effect.
• The command cannot be used to allocate a line in the mini Data Cache.
• The newly allocated line is not marked as "dirty" so it will never get evicted.
However, if a valid store is made to that line it will be marked as "dirty" and will get
written back to external memory if another line is allocated to the same cache
location. This eviction will produce unpredictable results.
To avoid this situation, the line-allocate operation should only be used if one of the
following can be guaranteed:
— The virtual address associated with this command is not one that will be
generated during normal program execution. This is the case when line-allocate
is used to clean/invalidate the entire cache.
— The line-allocate operation is used only on a cache region destined to be
locked. When the region is unlocked, it must be invalidated before making
another data access.
3.5.1.9

Register 8: TLB Operations

Disabling/enabling the MMU has no effect on the contents of either TLB: valid entries
stay valid, locked items remain locked. All operations defined in
regardless of whether the TLB is enabled or disabled.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
104
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Function opcode_2
0b000
0b000
0b001
0b000
0b001
0b001
0b100
0b110
0b101
Table 20
CRm Data
0b0111 Ignored
0b0101 Ignored
0b0101 MVA
0b0110 Ignored
0b0110 MVA
0b1010 MVA
0b1010 Ignored
0b0101 Ignored
0b0010 MVA
Chapter 3.0, "Data
®
Processor
work regardless of
Instruction
MCR p15, 0, Rd, c7, c7, 0
MCR p15, 0, Rd, c7, c5, 0
MCR p15, 0, Rd, c7, c5, 1
MCR p15, 0, Rd, c7, c6, 0
MCR p15, 0, Rd, c7, c6, 1
MCR p15, 0, Rd, c7, c10, 1
MCR p15, 0, Rd, c7, c10, 4
MCR p15, 0, Rd, c7, c5, 6
MCR p15, 0, Rd, c7, c2, 5
Cache".
Table 21 work
August 2006
Order Number: 306262-004US