Detailed Register Descriptions; Register Legend - Intel IXP45X Developer's Manual

Intel
Table 121. Configuration Controls (Sheet 2 of 2)
Constant
VUSB_HS_BANDWIDTH_TESTING
VUSB_HS_DEV_EP
VUSB_HS_NUM_PORT
VUSB_HS_TT_PERIODIC_CONTEXTS
VUSB_HS_RX_DEPTH
VUSB_HS_RX_BURST
VUSB_HS_TX_CHAN
VUSB_HS_TX_BURST
VUSB_HS_TX_LOCAL_
CONTEXT_REGISTERS
VUSB_HS_HCIVERSION
VUSB_HS_DCIVERSION
9.8

Detailed Register Descriptions

The MMR registers for the USB Host are (for the most part) EHCI specification
compliant, with exceptions as noted. The USB Host supports byte access to the MMR
space and the default access is "little-endian" after power-up or hardware reset. The
endian support for the MMR space is programmable which enables "big-endian" access.
This is important for byte access support and it is expected that one of the very first
operations being performed on the USB host is to correctly set the required endian
mode. Please see the USBMODE register description for details.
Table 122.

Register Legend

Attribute
RV
PR
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
364
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Controls the testing of the core. This constant should
always be zero.
Controls the maximum number of endpoints
supported by the core.
Controls the number of downstream ports in a host
implementation.
USB 2.0 specification requires a hub Transaction
Translator to have 16 periodic contexts. However, for
some host applications 4 may be adequate and a gate
count savings can be realized.
Controls the size of the receive latency buffer.
Controls the Bus burst size for Rx DMA data transfers.
Controls the size of each of the transmit latency
buffers.
Controls the Bus burst size for Tx DMA data transfers.
Determines if device transmit context registers are
implemented as a register file or stored in the TX-
FIFO.
Software readable host silicon version.
Software readable device silicon version.
Legend
Reserved
Preserved
Description
Attribute Legend
RC Read Clear
RO Read Only
Supported Values
0=Normal Bandwidth Testing
1=Bandwidth Starved
Testing (subset of Normal
Bandwidth Testing) Used for
system clock less than
30 MHz.
Integer values between 2
and 16. Set this to 1 for
single and multi-port host-
only products.
Integer values between 1
and 8. Set this to 1 for non-
multi-port products.
4 or 16.
Powers of 2 from 8 to 2048.
Integer values from 4 to
128.
Powers of 2 from 16 to 128.
Integer values from 4 to
128.
1=Implement device
transmit contexts in
registers. (Removes need for
read port A on TX-FIFO)
0=Store device transmit
contexts in TX FIFO.
(Smaller total gate count but
uses 4 words of
VUSB_HS_TX_CHAN per
endpoint)
Unsigned 16-bit integer.
Unsigned 16-bit integer.
August 2006
Order Number: 306262-004US