Tx Register Ready Bit (Tr); Conditional Execution Using Txrxctrl; Tx Handshaking; Txrxctrl Mnemonic Extensions - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
3.6.8.4

TX Register Ready Bit (TR)

The debugger and debug handler use the TR bit to synchronize accesses to the TX
register. The debugger and debug handler must poll the TR bit before accessing the TX
register.
Table 43.

TX Handshaking

Debugger Actions
• Debugger is expecting data from the debug handler.
• Before reading data from the TX register, the debugger polls the TR bit through JTAG until the bit is set.
NOTE: while polling TR, the debugger must scan out the TR bit and the TX register data.
• Reading a '1' from the TR bit, indicates that the TX data scanned out is valid
• The action of scanning out data when the TR bit is set, automatically clears TR.
Debug Handler Actions
• Debug handler wants to send data to the debugger (in response to a previous request).
• The debug handler polls the TR bit to determine when the TX register is empty (any previous data has
been read out by the debugger). The handler polls the TR bit until it is clear.
• Once the TR bit is clear, the debug handler writes new data to the TX register. The write operation
automatically sets the TR bit.
3.6.8.5

Conditional Execution Using TXRXCTRL

All of the bits in TXRXCTRL are placed such that they can be read directly into the CC
flags using an MCR instruction. To simplify the debug handler, the TXRXCTRL register
should be read using the following instruction:
mrc p14, 0, r15, C14, C0, 0
This instruction will directly update the condition codes in the CPSR. The debug handler
can then conditionally execute based on each C bit.
extension to conditionally execute based on whether the TXRXCTRL bit is set or clear.
Table 44.

TXRXCTRL Mnemonic Extensions

TXRXCTRL bit
31 (to N flag)
30 (to Z flag)
29 (to C flag)
28 (to V flag)
The following example is a code sequence in which the debug handler polls the
TXRXCTRL handshaking bit to determine when the debugger has completed its write to
RX and the data is ready for the debug handler to read.
loop: mcr p14, 0, r15, c14, c0, 0# read the handshaking bit in TXRXCTRL
mcrmi p14, 0, r0, c9, c0, 0 # if RX is valid, read it
bpl loop
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Table 43 shows the handshaking used to access the TX register.
Mnemonic Extension to Execute If Bit Set
# if RX is not valid, loop
Table 44
Mnemonic Extension to Execute If Bit
MI
EQ
CS
VS
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
shows the mnemonic
Clear
PL
NE
CC
VC
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